Semiconductor memory circuit having bit clear and/or register in

Details Semiconductor memory circuit having bit clear and/or register in Semiconductor memory circuit having bit clear and/or register in

1992-06-05

1995-03-28

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Erase

36518901, 365188, G11C 700

Patent

active

054023815

ABSTRACT:
A semiconductor memory circuit includes a plurality of memory cells arranged in an array form, a plurality of data lines for reading and writing data, a plurality of address lines each for transferring an address signal that specifies a corresponding specific memory cell, a control unit for controlling reading and writing of the data, a plurality of data input and data output terminals for inputting and outputting the data, a write enable signal input terminal to which a write enable signal for permitting writing of the data is applied, and at least one control signal input terminal to which either a cell clear signal for clearing the data stored or a cell initialization signal for performing the initialization of the data is applied. Data reading, data writing and data clearing or data initializing are performed through the plurality of data lines and the plurality of address lines. The hardware area to be occupied is reduced due to a reduction in the number of the cell transistors and also by a reduction in the number of signal lines.

REFERENCES:
patent: 4489404 (1984-12-01), Yasuoka
patent: 4879686 (1989-11-01), Suzuki et al.

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