Semiconductor memory circuit device having memory cells construc

Details Semiconductor memory circuit device having memory cells construc Semiconductor memory circuit device having memory cells construc

1991-02-26

1994-02-22

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

3652256, G11C 700

Patent

active

052894053

ABSTRACT:
A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array includes amplifying means constituted by a bipolar transistor connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means amplifies the potential level of readout data of the memory cell and output the same to an output line, thus enhancing the driving ability of the output line and reducing the whole readout time for reading out data from the memory circuit.

REFERENCES:
patent: 4995001 (1991-02-01), Dawson et al.
M. Kawauchi et al.., "A 1.Oum Compilable FIFO Buffer for Standard Cell," IEEE 1989 Custom Integ. Circuits Conf., May 15-18, 1989, pp. 23.4.1-23.4.4.
A 4-ns 4Kx1-bit Two-Port BiCMOS SRAM. IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988 by T. S. Yang, et al.

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