Semiconductor memory circuit and redundancy control method

Details Semiconductor memory circuit and redundancy control method Semiconductor memory circuit and redundancy control method

1999-05-24

2001-03-13

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189011

Reexamination Certificate

active

06201744

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory circuit having redundant memory cells for use in place of defective memory cells.
2. Description of the Related Art
In the manufacture of a memory device disposed on a semiconductor chip, small defects present in the chip frequently disable one or a few memory cells, while the other memory cells and circuits operate normally. Manufacturing yields can be improved if the chip is provided with redundant memory cells, which can be accessed in place of the defective memory cells.
Various redundancy schemes are known and used. Some schemes have redundant columns of memory cells; others have redundant rows of memory cells. Typical schemes employ a reconfiguration circuit that is programmed by means of laser-blown fuses, to determine whether redundant or non-redundant memory cells are accessed.
One conventional redundancy scheme provides redundant columns of memory cells, which are coupled to redundant sense amplifiers. The reconfiguration circuit is programmed to send enable signals to the line drivers that activate the sense amplifiers. When a column with a defective memory cell is addressed, the reconfiguration circuit disables the corresponding line driver and enables the line driver of a redundant column instead.
One problem with this replacement scheme is that it limits the access speed of the memory device, because the reconfiguration circuit must operate before activation of the sense amplifiers can begin. In memory devices that provide high-speed access to a plurality of memory cells, there are also timing problems caused by different signal propagation delays when the redundant column and the column it replaces are disposed in widely separated locations.
In a variation of this conventional scheme, the reconfiguration circuit operates by shifting columns so that when a column with a defective memory cell is accessed, it is replaced by the lower adjacent column, which is replaced by the next-lower column, and so on, the lowest column being a redundant column. This variation substantially eliminates the problem of timing differences, because each column is replaced by an adjacent column, but the problem of delayed sense amplification remains.
A further problem in these conventional replacement and shifting schemes occurs in memory devices permitting masked access such as write-per-bit access. In this case, besides controlling the column drivers, the reconfiguration circuit must perform a similar type of replacement or shifting control of the masking circuits.
Further information about these conventional schemes and their problems will be given following the detailed description of the invention.
SUMMARY OF THE INVENTION
An object of the present invention is to provide high-speed access in a semiconductor memory device having redundant memory cells.
Another object is to simplify masking control in a semiconductor memory device having redundant memory cells.
The invented method of controlling access to redundant and non-redundant memory cells in a semiconductor memory device comprises the steps of:
simultaneously activating a first sense amplifier coupled to a defective non-redundant memory cell and a second sense amplifier coupled to a redundant memory cell; and
switching data paths on a data bus to which the first and second sense amplifiers are coupled, thereby redirecting access from the defective non-redundant memory cell to the redundant memory cell.
The invented semiconductor memory device has a plurality of non-redundant sense amplifiers coupled to non-redundant memory cells, and at least one redundant sense amplifier coupled to a plurality of redundant memory cells. A data bus with switchable data paths is coupled to the redundant and non-redundant sense amplifiers. A redundancy control circuit receives an address signal, and switches the data paths on the data bus when a defective non-redundant memory cell is addressed, thereby redirecting access from the defective memory cell to a redundant memory cell. A driving circuit simultaneously activates both the redundant sense amplifier and the non-redundant sense amplifier to which the defective memory cell is coupled.
In a memory device having masking circuits, the switching circuits on the data bus paths are disposed between the masking circuits and the sense amplifiers.
The invented method and memory device provide high-speed access because activation of the sense amplifiers is not delayed by the switching of data paths.
Masking is simplified because the masking circuits operate in the same way, regardless of whether or not the data bus paths are switched.


REFERENCES:
patent: 6018483 (2000-01-01), Poechmueller et al.
patent: 6023433 (2000-02-01), Kashikawa
patent: 6078534 (2000-06-01), Pfefferl et al.

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