Semiconductor memory circuit and large scale integrated circuit

Details Semiconductor memory circuit and large scale integrated circuit Semiconductor memory circuit and large scale integrated circuit

1982-11-10

1986-04-29

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

For complementary information

365 63, 365 49, 307455, G11C 700, G11C 1140, G11C 1500

Patent

active

045861692

ABSTRACT:
A large scale integrated circuit including therein a logical gate circuit and a memory circuit is disclosed in which a large number of circuit blocks each having the same structure and including at least eight transistors and at least five resistors are arranged on a chip, and the logical gate circuit or memory circuit has a selected wiring pattern of the transistors and resistors included in the circuit block.

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Gonauser et al, "A Master-Slice Design Concept Based on Master Cells in ESFI-SOS-CMOS Technology", Siemens Forschungs-und Entwicklungsberichte, vol. 5, No. 6, pp. 344-349, 1976.
Braeckelmann et al, "A Subnanosecond Masterslice Array Offering Logic Plus Memory", IEEE ISSCC, Feb. 14, 1979, pp. 64-65.
Fields, "Low Voltage Memory Cell", IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, pp. 4555.

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