Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1980-10-17

1983-01-11

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365203, 365208, G11C 1140

Patent

active

043685293

ABSTRACT:
A semiconductor matrix circuit includes first and second matrix arrays of semiconductor memory cells, a plurality of sense amplifiers each having a flip-flop circuit, a plurality of first bit lines each commonly connected to memory cells in the same row of the first matrix array and also connected respectively to first bi-stable output terminals of the flip-flop circuits, and a plurality of second bit lines each commonly connected to memory cells in the same row of the second matrix array and also connected respectively to second bi-stable output terminals of the flip-flop circuits. Switching MOS transistors are each connected between the first and second bi-stable output terminals of a corresponding one of the flip-flop circuits. After a reading operation, the first and second bit lines are selectively set to high and low potential levels V.sub.D and V.sub.S, and subsequently all the switching MOS transistors are rendered conductive to set the potential on all the bit lines to an intermediate level (V.sub.D +V.sub.S)/2.

REFERENCES:
IEEE Journal of Solid State Circuits-vol. SC-11, No. 5, pp. 596-601., Oct. 1976.
Ieda et al., A 64K MOS RAM Design, Japanese Journal of Applied Physics, vol. 17, Supplement 17-1, pp. 57-63 (1978).

Affiliated with

Also associated with

Rating

Semiconductor memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-781376