Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2005-07-05
2005-07-05
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S203000
Reexamination Certificate
active
06914840
ABSTRACT:
Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.
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J. Barth, et al., “A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write”, ISSCC Digest of Technical Papers, U.S.A. ISSCC (International Solid-State Circuits Conference), Feb. 2002, pp. 156-157.
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