Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

2001-06-26

2003-02-18

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S189090, C365S189070

Reexamination Certificate

active

06522591

ABSTRACT:

The present application claims priority under 35 U.S.C. §119 to Japanese Application No. 2000-192582 filed on Jun. 27, 2000, which is incorporated herein by reference in its entirely for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the invention relates to a circuit, which detects a high voltage, and set a test mode of the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device has a test mode operation. When the test is performed, super high voltage is applied to a certain terminal. A voltage detecting circuit detects the super high voltage, and set the test mode of the semiconductor memory device.
FIG. 12
shows a conventional voltage detecting circuit. The voltage detecting circuit has a pad
1
, NMOS transistors
2
-
1
~
2
-n, a resistor
3
and an inverter
4
. Super high voltage is applied to the pad
1
. NMOS transistors and the resister are connected in series between the pad
1
and the ground voltage Vss. A node A between the transistor and the resistor
3
is connected to an input terminal of the inverter
4
.
When a voltage higher than the n times of threshold voltage (n*Vth) is applied to the pad
1
, the level of the node A is changed, and the inverter outputs L level., and the semiconductor memory device gets into a test mode.
However, the conventional voltage detecting circuit sometimes fails to set a test mode operation because of the manufacturing error of the threshold voltage.
SUMMARY OF THE INVENTION
A semiconductor memory device includes a reference voltage circuit being inputted external power supply voltage, and outputting a reference voltage, a standard voltage circuit being inputted the reference voltage, and outputting a standard voltage, a PMOS transistor having a gate, a source and a drain, the gate being connected to the standard voltage, a source being electrically connected to a pad, and a drain being connected to the ground voltage via a resistor and a test mode control circuit outputting a test mode operation signal, an input terminal of the test mode control circuit being connected to a node between the transistor and the resistor.


REFERENCES:
patent: 5563546 (1996-10-01), Tsukada
patent: 5929696 (1999-07-01), Lim et al.
patent: 6078210 (2000-06-01), Uchida et al.
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patent: 6-119798 (1994-04-01), None
patent: 6-224648 (1994-08-01), None
patent: 8-51457 (1996-02-01), None
patent: 10-106299 (1998-04-01), None
patent: 10-116129 (1998-05-01), None
patent: 10-289577 (1998-10-01), None

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