Semiconductor memory circuit

Static information storage and retrieval – Read/write circuit – Differential sensing

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365104, 365208, G11C 700, G11C 1700

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043887058

ABSTRACT:
A semiconductor memory circuit (10) has a plurality of word lines (12, 14), column lines (16, 18) and bit lines (20, 22). A memory cell transistor (30) has the gate terminal connected to the word line (12) and the drain and source terminals connected between the bit line (20) and the column line (16). A reference transistor (106) is connected to the word line (12) to provide a reference signal for input to a sense amplifier (136). A data line (54) is connected to the bit line (20) to provide the data state from the data storage transistor (30) to the sense amplifier (136). The data bit line (20) and reference bit line (104) are clamped at different pull down voltages. The memory circuit (10) includes a reference circuit that has reference transistor (106) which operates statically to provide a reference signal for the sense amplifier (136). When the word lines are being sequentially accessed the reference signal produced by the reference circuit rises to a higher average voltage and enhances the operating speed of the memory.

REFERENCES:
patent: 4107548 (1978-08-01), Sakaba et al.
patent: 4150311 (1979-04-01), Matsuda et al.
patent: 4162416 (1979-07-01), Beecham et al.
patent: 4196363 (1980-04-01), Malaviya
patent: 4314360 (1982-02-01), Higuchi et al.
IBM Technical Disclosure Bulletin, vol. 24, No. 10, Mar. 1982, pp. 5165-5166, "Dummy Word Decoder", Mao et al.

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