Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1998-10-26

2000-06-06

Le, Vu A.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, 365204, G11C 700

Patent

active

060727314

ABSTRACT:
When the data read out line is in the non-selective state, the data select line is at the "L" level, and therefore, the NMOS transistor is turned on, and to the data read out line, the capacity of the condenser is added. Therefore, the potential rising of the data read out line because of the influence of the coupling capacity just after the data select line has become at the "H" level, is small. After that, the memory cell data is transmitted to the data read out line, but at this time, the NMOS transistor becomes in the off state, and therefore, the capacity of the data read out line is reduced, so that the read out speed of the data may not be affected. Consequently, the signal interference because of the coupling capacity can be reduced.

REFERENCES:
patent: 5491453 (1996-02-01), Mun et al.
patent: 5805515 (1998-09-01), Suzuki

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