Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1980-10-16

1983-09-13

Stellar, George G.

Static information storage and retrieval

Systems using particular element

Flip-flop

G11C 1140

Patent

active

044046570

ABSTRACT:
A semiconductor memory circuit includes a power supply terminal; a first MOS transistor; a second MOS transistor whose source, gate and drain are respectively connected to the source, drain and gate of the first MOS transistor; first and second resistors connected between the power supply terminal and the drains of the first and second MOS transistors; a data line; a word line; and a third MOS transistor whose current path is connected between the drain of the first MOS transistor and data line, and whose gate is connected to the word line. The semiconductor memory circuit further includes a write control line whose potential is set at a high level when a readout operation is effected. The sources of the first and second MOS transistors are jointly connected to the write control line.

REFERENCES:
patent: 3191061 (1965-06-01), Weimer
patent: 3447137 (1969-05-01), Feuer
patent: 3644907 (1972-02-01), Gricchi et al.
patent: 3813653 (1974-05-01), Smith et al.
patent: 4134151 (1979-01-01), O'Connell et al.
IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 180-186, Memory Cell Adapted for Different Combinations of Simultaneous Read and Write Operations, J. R. Cavaliere et al.
IBM Technical Disclosure Bulletin, vol. 14, No. 6, Nov. 1971, p. 1693, Storage Cell With Single Bit Line, R. D. Moore.
Roger G. Stewart and Andrew G. F. Dingwall, 16K CMOS/SOS Asynchronous Static RAM, 1979 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 104-105, (Feb. 15, 1979).

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