Semiconductor memory chip

Details Semiconductor memory chip Semiconductor memory chip

2005-10-04

2008-08-19

Sough, Hyung S. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C365S230030, C365S189050

Reexamination Certificate

active

07415581

ABSTRACT:
A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

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