Semiconductor memory cell with clocked voltage supply from data

Details Semiconductor memory cell with clocked voltage supply from data Semiconductor memory cell with clocked voltage supply from data

1980-05-12

1982-06-08

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, 365222, G11C 700, G11C 1140

Patent

active

043342930

ABSTRACT:
An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. The coupling transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.

REFERENCES:
patent: 3550097 (1970-12-01), Reed
patent: 4103185 (1978-07-01), Denes
Miller, COS/MOS Random Access Memories, IEEE Digest, pp. 34-35, 3/71.

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