Semiconductor memory cell having read/write circuit capable...

Details Semiconductor memory cell having read/write circuit capable... Semiconductor memory cell having read/write circuit capable...

2000-11-22

2001-10-23

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S205000, C365S189011

Reexamination Certificate

active

06307788

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory cells configured by semiconductor devices such as MOS transistors.
This application is based on Patent Application No. Hei 10-177763 and Patent Application No. Hei 10-204048 both filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventionally, the semiconductor memory cells are configured using MOS transistors (where “MOS” is an abbreviation for “Metal-Oxide Semiconductor”). For example,
FIG. 10
shows a memory cell of a three-transistor type, which uses three n-channel MOS transistors.
Concretely speaking, the memory cell of
FIG. 10
is mainly configured by a transistor
1
used for write control, a transistor
2
having capacitance (or capacity) C for accumulating (electric) charges at its gate, and a transistor
3
used for read control.
As for the transistor
1
, a gate is connected to a write word line WWrd, a drain is connected to a write bit line WBit, and a source is connected to the gate of the transistor
2
. Herein, the write bit line WBit is set at a level corresponding to write data. As for the transistor
2
, a source is grounded while a drain is connected to a source of the transistor
3
. As for the transistor
3
, a gate is connected to a read word line RWrd, while a drain is connected to a read bit line RBit used for read operations.
Next, a description will be given with respect to operations of the memory cell of FIG.
10
. At a write mode, a high (logical) level (or H level) is applied to the write word line WWrd, so that the transistor
1
is turned on. Thus, electric charges corresponding to the level of the write bit line WBit are accumulated at the gate of the transistor
2
. That is, the charges are accumulated at the gate of the transistor
2
when the write bit line WBit is at the H level, while the charges are not accumulated at the gate of the transistor
2
when the write bit line WBit is at a low (logical) level (or L level).
At a read mode, the read bit line RBit is pre-charged, in other words, the H level is applied to RBit, thereafter, the H level is applied to the read word line RWrd.
In this case, if the memory cell accumulates the charges, the transistors
2
and
3
are turned on. As a result, the read bit line RBit is changed in level from the H level due to the pre-charging to the L level corresponding to the ground level.
If the memory cell does not accumulate the charges, the transistor
2
remains “off”, so the read bit line RBit remains at the H level due to the pre-charging.
In short, in response to the charges accumulated in the memory cell, the level of the read bit line RBit is changed to the L level, or it is maintained at the H level. Thus, it is possible to actualize storage of data in the memory cell. In the present description, accumulation of charges at the gate will be referred to as writing of data “0” into the memory cell. For this reason, an event that the level of the read bit line RBit is changed to the L level will be referred to as an event that the data “0” is read from the memory cell.
By the way, due to “junction leak” and “sub-threshold leak”, the charge s (or data) accumulated in the memory cell disappear over a lapse of time. Particularly, sub-threshold current of the transistor
1
increases exponentially against gate voltage. So, it is easily influenced by (states of) the write word line WWrd supplying the gate voltage.
In general, a number of memory cells are arranged in a matrix form to construct a cell array. Herein, the memory cells disposed in a same column in the cell array share a bit line, while the memory cells disposed in a same row share a word line.
When variations occur on the level of the write word line WWrd due to interference which is caused by access to other memory cells, variations occur remarkably on amounts of leaked charges with respect to all of the memory cells connected to the write word line WWrd. On the other hand, amounts of leaked charges remain constant with respect to the memory cells connected to the write word line which is not varied in level. For this reason, the memory cells differ from each other in amounts of leaked charges. This means that the cell array as a whole is very unstable in operations.
FIG. 11
shows another example of the memory cell, which is a modification of the aforementioned memory cell of FIG.
10
. That is, the memory cell of
FIG. 10
is modified in such a way that the write bit line WBit and the read bit line RBit are shared by a single bit line Bit. As compared with the memory cell of
FIG. 10
, the memory cell of
FIG. 11
is advantageous in that when being integrated, a chip area can be reduced.
By the way, the charges (or data) accumulated at the gate of the transistor leak over a lapse of time. In order to maintain the charges, it is necessary to perform injection of charges every prescribed time. Such operation regarding the injection of charges is referred to as “refresh” in general.
Next, a description will be given with respect to the refresh, which is mainly performed in three steps as follows:
(1) The read bit line RBit or the bit line Bit is pre-charged.
(2) The H level is applied to the read word line RWrd so as to make a decision as to level transition in the read bit line RBit or the bit line Bit.
(3) The H level is applied to the write word line WWrd, and a signal having an inverse level of the bit line after the level transition is applied to the write bit line WBit or the bit line Bit.
In the case of the memory cell of
FIG. 10
, for example, the refresh is made by using an inverter
4
, which is introduced between the bit lines WBit and RBit as shown in FIG.
12
. That is, the inverter
4
inverts the level of the read bit line RBit, so that the inverted level is applied to the write bit line WBit. Thus, it is possible to rewrite the charges to the same memory cell.
As described above, in order to refresh the data of the memory cell, it is necessary to provide at least three steps, i.e., pre-charge step of the read bit line, data read step and data rewrite step. Herein, the pre-charge step of the read bit line cannot be performed simultaneously with the data read step. For this reason, it is necessary to provide a specific duration for the pre-charging. This causes a trouble in efficient use of the memory cell. Such a trouble becomes remarkable in the case of the memory cell which is designed to share the read and write bit lines by a single bit line as shown in FIG.
11
.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor memory cell which is stabilized in amounts of accumulated charges by suppressing level variations of write word lines, due to random access, to the minimum.
It is another object of the invention to provide a read/write circuit for the semiconductor memory cell which is capable of performing random access, wherein the data read step and data rewrite (or refresh) step can be performed efficiently without using the specific duration for the pre-charging.
A semiconductor memory cell of this invention is configured using a sense amplifier and a memory cell, which is configured using MOS transistors, for example. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Or, a single bit line is shared by the memory cells which are arranged in the same column. Further, the sense amplifier is connected with the pair

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