Semiconductor memory cell device having dummy capacitors reducin

Details Semiconductor memory cell device having dummy capacitors reducin Semiconductor memory cell device having dummy capacitors reducin

1993-03-26

1994-11-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

257303, 257306, 257296, G11C 1300

Patent

active

053612345

ABSTRACT:
A semiconductor memory device comprises a plurality of word lines, a plurality of digit lines, a peripheral circuit area and a memory cell array area. The memory cell array area comprises a semiconductor substrate having a surface in which field oxide films are selectively formed, a plurality of operational memory cells arrayed on active regions within the memory cell array area, each of which includes a stacked capacitor and a switching transistor, and a plurality of dummy capacitors arranged within the memory cell array area at an adjacent portion to a boundary area between the memory cell array area and the peripheral circuit area. The dummy capacitor is to receive affections caused by an inferiority of the accuracy of patterning by a photolithography in replacement of the operational memory cells. The dummy capacitor is so formed over the field oxide film as to prevent said digit line at said boundary area to have a rapid slope or a large difference in level.

REFERENCES:
"A Half Micron Technology For An Experimental 16MBIT Dram Using i-Line Stepper", By Y. Kawamoto et al., pp. 17-18.
"3-Dimensional Stacked Capacitor Cell For 16M and 64M Drams" 1988 IEEE, By T. Ema et al., p. 592.
"Buried Bit-Line Cell for 64MB Drams", 1990 IEEE, By Y. Kohyama et al., p. 17.

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