Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-02-08
2005-02-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S774000, C438S242000, C438S243000, C438S386000
Reexamination Certificate
active
06853023
ABSTRACT:
A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.
REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
patent: 4937641 (1990-06-01), Sunami et al.
patent: 4967247 (1990-10-01), Kaga et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5989972 (1999-11-01), Widmann et al.
patent: 6373099 (2002-04-01), Kikuchi et al.
patent: 20020017671 (2002-02-01), Goebel et al.
patent: 198 45 004 (2000-04-01), None
patent: 198 45 058 (2000-04-01), None
patent: 199 23 262 (2000-06-01), None
patent: 62140456 (1987-06-01), None
patent: 63240061 (1988-10-01), None
patent: 05291528 (1993-11-01), None
patent: 0033383 (2000-06-01), None
patent: 0117015 (2001-03-01), None
Goebel Bernd
Lützen Jörn
Popp Martin
Seidl Harald
Nelms David
Tran Long
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