Semiconductor memory cell

Details Semiconductor memory cell Semiconductor memory cell

1988-03-30

1990-02-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365194, 365195, G11C 800

Patent

active

049051920

ABSTRACT:
A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.

REFERENCES:
patent: 4723227 (1988-02-01), Murotani
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs," ISSCC Digest of Technical Papers, Feb. 1981, pp. 80-81.
Eaton et al., "A 100ns 64K Dynamic RAM Using Redundancy Techniques," ISSCC Digest of Technical Papers, Feb. 1981, pp. 84-85.

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