Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-06-15
2001-03-13
Cady, Albert De (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000
Reexamination Certificate
active
06202180
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
Discussion of the Background
A method has heretofore has been adopted, in which in order to relieve errors of semiconductor memories, spare row and column lines are additionally provided previously and the errors of the semiconductor memories are relieved by replacing row or column lines of defect memory cells regarded as faulty ones because of their errors.
The foregoing conventional method requires the semiconductor memory to provide the spare lines, resulting in a problem of a large chip size. In order to replace the row and column lines of the faulty memory cell with the spare line, it is necessary to write programs using fuses when a wafer test is conducted, and testing equipment for it is needed. Moreover, since there is sometimes a case where excessive processes must be conducted for an element for the fuse, leading to an increase in manufacturing cost. Besides the foregoing spare memory, as a error relief technology, there are also memory using an ECC (Error Checking and Correcting) technology, in which erroneous data is replaced with corrected data even when errors exist. This memory with ECC involves a problem that it has a memory capacitance larger than an original capacitance and has a large size chip because of addition of an ECC circuit. For example, in case of a 16M memory, the memory capacitance increases by 11 to 12%.
SUMMARY OF THE INVENTION
The present invention was made from viewpoint of such circumstances, and the object of the present invention is to provide a memory for controlling a display which is capable of relieving a memory cell simply by exchanging addresses without addition of a spare memory and an ECC circuit when errors exist in a memory. Furthermore, the object of the present invention is to provide a memory for controlling a display which is capable of relieving a memory cell by exchanging addresses with a high efficiency when errors exist in a memory.
To achieve the above object, the present invention provides a memory control circuit for a display comprising an external address input; a first memory circuit which stores address corresponding to a predetermined portion in a display; a second memory circuit which stores address found to be faulty as a result of testing; and address changing means coupled to the foregoing external address input and the foregoing first and second memory circuits, the address changing means outputting the address stored in the foregoing second memory circuit when address inputted thereto from the foregoing external address input is coincident with that stored in the foregoing first memory circuit, and outputting the address stored in the foregoing first memory circuit when the address inputted thereto from the foregoing external address input is coincident with that stored in the foregoing second memory circuit.
Other objects, features and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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Cady Albert De
Chase Shelly A
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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