Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-12-17
2003-03-18
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S221000, C365S185010, C365S189030, C365S239000
Reexamination Certificate
active
06535442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory that operates in accordance with a command supplied from the exterior of the memory.
2. Description of the Related Art
A semiconductor memory such as a flash memory or the like decodes control signals supplied via a plurality of external terminals to thereby recognize a command supplied form the exterior. An internal circuit in the memory operates, in response to the recognized command, to execute a read, write or erase operation. The statuses of the write and erase operations are transmitted to the exterior via a status terminal. As this status terminal, for example, a dedicated terminal such as a ready/busy terminal or a shared terminal such as a data input/output terminal may be used. A system mounting the flash memory can recognize, in accordance with information transmitted via the status terminal, the status of the flash memory and the result of a verify during a write operation.
As having nonvolatile memory cells, the flash memory is often used so as to store the program of a CPU for controlling the system or store data that are rewritten with little frequency.
If a system malfunction or the like occurs, causing the data stored in a program or data area of the flash memory to be overwritten or erased, then it may stop the system from operating. In such a case, since the program and data areas allocated in the flash memory are nonvolatile, the original state cannot be recovered even after powering the system off and on again.
Such a situation will occur with great frequency during development of a system mounting the flash memory, such as a cellular phone or the like. Specifically, during a debug of the system, the system would be disabled from normally operating if a problem occurring in a software causes data to be written into a program area of the flash memory. In such a case, the system developer compares the contents of the program area with respective expected values one by one to thereby locate the area where the incorrect data are written and determine the data value. However, even if successfully recognizing the area where the incorrect data are written and the data value, the system developer often cannot figure out the cause of the foregoing problem. For this reason, the occurrence of the foregoing problem significantly reduces the system debug efficiency.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory that allows easy clarification of the cause of problems that a system or the like mounting the semiconductor memory has done an incorrect write to or an incorrect erase from the semiconductor memory.
According to one of the aspects of the present invention, when a command is supplied so as to execute a memory operation, a command storing control circuit stores in storing units a plurality of commands supplied the latest of the supplied commands, by controlling the command storing area. For example, if a malfunction of the system mounting the semiconductor memory causes incorrect data to be written into the semiconductor memory or data stored in the semiconductor memory to be incorrectly erased therefrom, the state of the semiconductor memory is shifted to a test mode. In response to this shift to the test mode, a command reading control circuit controls the command storing area to read the commands stored therein. Thereafter, a system developer or the like analyzes the commands stored in the command storing area to determine the cause of the trouble.
Thus tracking, in the order of time series, the processes of the write and erase operations of the semiconductor memory can efficiently determine the cause of the trouble. As a result, the efficiency of development of the system mounting the semiconductor memory can be improved, for example, and the cost of developing the system can be reduced. Moreover, the quality of the system can be also improved.
According to another aspect of the present invention, when receiving via an external terminal a voltage that is not supplied in a normal operation mode executing the memory operation, the semiconductor memory gets into the test mode, activating the reading control circuit. Operating the reading control circuit only in the test mode prevents commands from erroneously being read from the command storing area during execution of the normal operation.
According to another aspect of the present invention, the storing units include electrically rewritable nonvolatile elements, so that even if the power supply is cut off, the commands can be held. Accordingly, even if incorrect data are written into the semiconductor memory, causing the system mounting the semiconductor memory to become inoperable, for example, powering the system on again allows the commands stored in the storing units to be read therefrom without fail.
According to another aspect of the present invention, the command storing control circuit sequentially stores the commands in the command storing area. After the number of the empty units in the storing units with no commands stored becomes one, every time a command is supplied anew, the command is stored in the empty unit, and the oldest command is erased at the same time to reserve an empty unit anew. As a result, the empty unit can be utilized as a pointer that indicates the storing unit where the latest command is stored, whereby the order the commands stored in the command storing area were supplied can be easily recognized.
According to another aspect of the present invention, every time a command is supplied anew, data are read from all the storing units in the command storing area, whereby the empty units can be easily detected by simply controlling the command storing control circuit.
According to another aspect of the present invention, the command storing control circuit sequentially stores the commands in the command storing area. After the commands are stored in all the storing units of the command storing area, each time a command is supplied anew, the oldest command is erased to reserve an empty unit, in which the command supplied anew is stored. For example, the storing unit where the latest command is stored is recognized by use of a pointer, thereby improving the storing efficiency of the command storing area.
REFERENCES:
patent: 5917438 (1999-06-01), Ando
patent: 7-192479 (1995-07-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Tran Andrew Q.
LandOfFree
Semiconductor memory capable of debugging an incorrect write... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory capable of debugging an incorrect write..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory capable of debugging an incorrect write... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3045957