Semiconductor memory asynchronous pipeline

Details Semiconductor memory asynchronous pipeline Semiconductor memory asynchronous pipeline

2007-02-13

2007-02-13

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C711S167000, C713S400000, C713S401000, C713S500000, C365S233100, C365S233500

Reexamination Certificate

active

10855968

ABSTRACT:
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

REFERENCES:
patent: 4658354 (1987-04-01), Nukiyama
patent: 5272390 (1993-12-01), Watson, Jr. et al.
patent: 5294842 (1994-03-01), Iknaian et al.
patent: 5402388 (1995-03-01), Wojcicki et al.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5550784 (1996-08-01), Takai
patent: 5579267 (1996-11-01), Koshikawa
patent: 5655105 (1997-08-01), McLaury
patent: 5666480 (1997-09-01), Leung et al.
patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5713005 (1998-01-01), Proebsting
patent: 5784705 (1998-07-01), Leung
patent: RE35934 (1998-10-01), Takai
patent: 5835443 (1998-11-01), Fujita
patent: 6014339 (2000-01-01), Kobayashi et al.
patent: 6078546 (2000-06-01), Lee
patent: 6539454 (2003-03-01), Mes
patent: 0 704 848 (1996-04-01), None
patent: 09 091955 (1997-04-01), None
Boerno, Lopez-Buedo and Meneses, “The Wave Pipeline Effect on LUT-based FPGA Architectures”, Ciudad Universitaria, Madrid, Spain.
Mehrdad Heshami et al., “A 250-MHz Skewed—Clock Pipelined Data Buffer”, IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1, 1996, pp. 376-383.

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