Semiconductor memory array of floating gate memory cells...

Details Semiconductor memory array of floating gate memory cells... Semiconductor memory array of floating gate memory cells...

2005-03-29

2005-03-29

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000, C257S622000, C438S689000

Reexamination Certificate

active

06873006

ABSTRACT:
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

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