Semiconductor memory array having interdigitated bit-line struct

Details Semiconductor memory array having interdigitated bit-line struct Semiconductor memory array having interdigitated bit-line struct

1992-02-24

1993-05-25

Bowler, Alyssa H.

Static information storage and retrieval

Format or disposition of elements

365 63, 365207, 36518901, G11C 506, G11C 700, G11C 11407

Patent

active

052146006

ABSTRACT:
Disclosed is a layout method for increasing pitches between bit lines and between sense amplifiers so as to easily accomplish fabrication of a semiconductor memory device and a semiconductor memory array capable of reducing the number of sense amplifiers. The semiconductor memory array includes a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier being connected to each pair of the bit lines, wherein the sense amplifiers placed in each column make up each group, with odd pairs of the bit lines being connected to even or odd sense amplifier groups, and even pairs of the bit lines being connected to even or odd sense amplifier groups.

REFERENCES:
patent: 4456977 (1984-06-01), Hayashi
patent: 4586171 (1986-04-01), Fujishima
patent: 4733374 (1988-03-01), Furuyama
patent: 4761571 (1988-08-01), Golke et al.
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 4903344 (1990-02-01), Inoue
patent: 5014241 (1991-05-01), Asakura et al.

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