Semiconductor memory array

Details Semiconductor memory array Semiconductor memory array

1980-06-18

1982-07-27

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365104, 365210, G11C 700

Patent

active

043421024

ABSTRACT:
An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.

REFERENCES:
patent: 3614750 (1971-10-01), Janning
patent: 3938108 (1976-02-01), Salsbury et al.
patent: 4031524 (1977-06-01), Heeren
patent: 4094008 (1978-06-01), Lockwood _et al.
Varshney, "Leakage-Compensated Reference Voltage Generator", IBM Tech. Disc. Bul., vol. 22, No. 8A, 1/80, pp. 3237-3238.
Wilson et al., "A 100ns 150mW 64Kbit ROM", Digest of Tech. Papers, ISSCC 1978, 2/16/78, pp. 152, 153, 273.

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