Semiconductor memory arrangement with branched control and...

Details Semiconductor memory arrangement with branched control and... Semiconductor memory arrangement with branched control and...

2005-09-15

2008-08-12

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S051000, C365S063000

Reexamination Certificate

active

07411843

ABSTRACT:
A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

REFERENCES:
patent: 6078965 (2000-06-01), Mellitz et al.
patent: 7184360 (2007-02-01), Gregorius et al.
patent: 7242213 (2007-07-01), Pax et al.
patent: 7245145 (2007-07-01), Pax et al.
patent: 2006/0291263 (2006-12-01), Wallner et al.

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