Semiconductor memory architecture

Details Semiconductor memory architecture Semiconductor memory architecture

2001-10-05

2003-06-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S230040

Reexamination Certificate

active

06580637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor memories, particularly but not exclusively to non-volatile memories, for example, Flash EEPROM memories (hereinafter referred to as Flash memories).
2. Description of the Related Art
The typical structure of the simplest non-volatile semiconductor memories such as ROMs and EPROMs comprises basically a matrix of memory cells (the memory matrix) in which the cells are arranged in rows (“word lines”) and columns (“bit lines”), circuits for decoding an address supplied from the exterior, circuits for selecting the memory cells within the matrix in dependence on the address supplied from the exterior, circuits for reading the contents of the memory cells selected, and output circuits for driving external data lines.
In a conventional non-volatile memory, the sole type of reading access to the memory is random access. The address of the memory location the content of which is to be read is supplied to the memory from the exterior. The decoding circuits and the selection circuits, respectively, decode the address supplied from the exterior and select the memory cells which correspond to that address, that is, they select the rows and the columns. The reading circuits read the contents of the memory cells selected and supply the result of the reading to the output circuits; the datum read in the memory location addressed is placed on the data lines outside the memory.
During random access to the memory, the time required to perform the reading (the memory-access time) is the sum of individual times representative of the durations of the various individual steps which make up the access and datum-extraction process. Basically, these individual steps are: the propagation of the signals along the row and column selection paths, precharging operations, for example, of the columns selected, the step of reading and evaluating the data stored in the memory cells selected, the propagation and transfer of the data read to the output (“buffer”) circuits, and the switching thereof.
Each random-access operation involves the execution of all of the above-mentioned individual steps. Precisely for this reason, the access time is quite long or, in any case, is difficult to reduce, even with the use of advanced manufacturing technologies. In particular, the memory-access time for a random reading is longer than the time which is strictly necessary to perform the reading of the content of a memory location.
However, whilst having an access time which is not optimal, the conventional architecture has the advantage that it is straightforward in terms of internal circuit structures and simple from the point of view of the timing (the memory behaves asynchronously), that it can be used relatively easily for the implementation of redundancy structures for “functionally repairing” memory elements which are not operating, and that it has low consumption.
Some producers of integrated circuits have proposed an architecture for nonvolatile memories, particularly ROMs (“Mask ROMs”), which is known in the art as “Page Mode,” and which enables performance to be improved in terms of memory-access time. This architecture permits parallel reading of several memory locations (for example, eight bytes or words) in a first reading cycle; the result of the parallel reading of the eight memory locations is stored in a package of a corresponding number of holding registers; the content of a preselected one of the registers of the package is then made available to the exterior.
With this technique, it is possible to scan the eight memory locations read in parallel, the contents of which are stored in the respective registers of the package, within a time significantly less than (approximately half of) the time required to complete a random-access reading. However, the first reading cycle, during which the eight locations are read in parallel, has a duration corresponding to that of a random-access reading. In the best case, therefore, a slower random-access reading is necessarily provided for every eight rapid readings.
Other disadvantages of “page mode” architecture lie in the large number of reading circuits which are required to read the eight locations in parallel (eight times the number normally required), in the high current-absorption during the reading of the eight memory locations in parallel, in the need to provide the package of holding registers, in the need to provide circuits for decoding and selecting the individual registers in the package, and in the management of a memory-reading protocol which provides for a double cycle time (“random” and “page mode”). Moreover, in comparison with conventional architecture “page mode” architecture reduces the efficacy of the redundancy structures. In fact, it is very difficult and, in any case, extremely complex from the point of view of the resulting structure, to provide for the capability to select several redundancy rows or columns simultaneously, which would be necessary if, amongst the eight memory locations to be read in parallel, there were some which belonged to two or more different defective lines or to two or more different defective columns.
BRIEF SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a memory architecture that enables the reading performance of the memory to be improved in comparison with conventional architectures, whilst reducing the disadvantages of “page mode” architecture.
According to an embodiment of the present invention, a semiconductor memory architecture comprising two memory banks each containing respective memory locations is provided. The architecture includes:
for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank,
a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure that can be assigned selectively to one memory bank at a time and which comprises storage means for storing the most recent datum read by the reading circuits, and output driver circuits that can be activated selectively in order to transfer the contents of the registers to the data output terminals of the memory,
an addressing structure comprising, for each memory bank, a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the bank,
first circuit means for initializing the sequential scanning circuits by means of an address supplied from outside the memory and corresponding to an origin location, the first circuit means being sensitive to a first control signal from outside the memory and indicative of the presence of the address corresponding to the origin location,
second circuit means for bringing about a selective updating of the sequential scanning circuits so as to bring about, starting from the origin location, sequential access to further locations addressed by the addressing structure by accessing the memory banks alternately, by an interleaved method,
third circuit means for managing the reading circuits of the two memory banks in accordance with the interleaved method so that two reading processes are executed contemporaneously, but suitably offset in time, in the two memory banks,
fourth circuit means for bringing about the selective assignation of the data-transfer structure to the memory bank currently being accessed, in accordance with the interleaved method, and
an internal timing structure for controlling the first, second, third, and fourth circuit means, the data-transfer structure, and the addressing structure, in accordance with second control signals from outside the memory.


REFERENCES:
patent: 6021077 (2000-02-01), Nakaoka
patent: 6259627 (2001-07-01), Wong
patent: 6356506 (2002-03-01), Ryan

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