Semiconductor memory architecture for minimizing...

Details Semiconductor memory architecture for minimizing... Semiconductor memory architecture for minimizing...

2001-04-10

2002-05-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S189020

Reexamination Certificate

active

06396766

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates generally to high-speed memory devices and, in particular, to semiconductor memory architectures that minimize I/O (input/output) data paths and differences between the I/O data paths.
2. Description of the Related Art
In general, a synchronous dynamic random access memory (SDRAM) receives and outputs data in synchronization with a strobe signal and a system clock signal. A SDRAM typically comprises at least two banks and a plurality of peripheral circuits for the memory cells that are installed in symmetry to each other with respect to all banks.
FIG. 1
is a diagram illustrating a pin configuration of a conventional SDRAM chip. Further,
FIG. 2
is a block diagram illustrating an architecture of the SDRAM having the pin configuration shown in FIG.
1
. The pin layout of
FIG. 1
, which is defined by the JEDEC (Joint Electron Device Engineering Council) standard, illustrates the pin layout for pins corresponding to addresses A
0
through A
11
, commands such as CAS (column address strobe), RAS (row address strobe), and data pins DQ
0
through DQ
15
.
In
FIG. 2
, the SDRAM architecture comprises four banks A through D, which are located adjacent to each other, and a DB/MUX
1
, which serves as both a data buffer and a multiplexer, located between banks A and B and banks C and D. The DB/MUX
1
operatively connects the four banks A, B, C, D to each other and operatively connects data paths DQ
0
through DQ
15
to each other.
Each of the four banks A, B, C and D comprise a pair of blocks A
1
-A
2
, B
1
-B
2
, C
1
-C
2
and D
1
-D
2
. Each of the blocks comprises a number of I/O sense amplifiers (IOSAs) that is equal to the number of output data. As is known in the art, the sense amplifiers are used for sensing and amplifying the state of data.
In the four banks A, B, C, D, the odd-numbered blocks A
1
, B
1
, C
1
, D
1
each comprise a plurality of cells representing 8-bit data of DQ
0
through DQ
7
among 16-bit data of DQ
0
through DQ
15
. Further, the even-numbered blocks A
2
, B
2
, C
2
, D
2
each comprise a plurality of cells representing 8-bit data of DQ
8
through DQ
15
among the 16-bit data of DQ
0
through DQ
15
.
A plurality of pads DQ
0
through DQ
15
connected to the DB/MUX
1
comprise two groups of pads—a first group which inputs/outputs a total of 8 bits DQ
4
through DQ
11
, and a second group which inputs/outputs a total of 8 bits DQ
0
through DQ
3
and DQ
12
through DQ
15
.
During operation of the SDRAM (of FIGS.
1
and
2
), signals from the address pads and command pads that are located on one side of the chip must be propagated to corresponding memory cells after passing through the center of a chip, and the data output from the memory cells must be propagated to the data paths located at the other side of the chip. As SDRAM chips are enlarged, the overall performance of a circuit depends not only on the size and performance of a single transistor, but also on the time for propagating signals along the wiring of the circuit. Thus, a circuit comprising long data transmission paths can degrade the overall performance of an SDRAM. For instance, as shown in
FIG. 2
, a long data path (indicated by bold arrows) can significantly prolong the time for propagating a specific signal. Further, the difference between the long data path and a short data path (indicated by a dotted arrow) can be significant.
Accordingly, a semiconductor architecture that provides a reduction in the length of the data paths in a SDRAM is highly desirable. Although this reduction may be accomplished by changing the pin configuration of a memory integrated circuit, this is not preferable since modifications to the pin configuration of standard memory integrated circuits would render such chips incompatible with existing systems.
SUMMARY OF THE INVENTION
The present invention is directed to semiconductor memory devices having an architecture that minimize the I/O data paths and the differences between such data paths. In one aspect of the present invention, a semiconductor memory device comprises:
a plurality of pad groups each comprising a plurality of data I/O (input/output) pads;
a plurality of banks, wherein each bank comprises a plurality of blocks of memory cells and a plurality of I/O units for sensing and amplifying the state of data output from the memory cells; and
a plurality of circuits connected between the plurality of banks and the plurality of pad groups for performing multiplexing.
In another aspect, the pad groups comprise a first pad group and a second pad group. The first pad group is preferably located in proximity to the center of the semiconductor device, and comprises a first portion of a total number of data I/O pads. The second pad group comprises a second portion of the total number of data I/O pads. Preferably, the first and second pad groups comprise an equal number of pads.
In yet another aspect, the plurality of banks comprise a first, second, third and fourth bank. The first bank comprises a first block of memory cells, a second block of memory cells, a first I/O unit comprising a plurality of sense amplifiers, and a second I/O unit comprising a plurality of sense amplifiers. The second bank comprises a third block of memory cells, a fourth block of memory cells, a third I/O unit comprising a plurality of sense amplifiers and a fourth I/O unit comprising a plurality of sense amplifiers. The second bank is preferably located adjacent to the first bank on the semiconductor memory device. The third bank comprises a fifth block of memory cells, a sixth block of memory cells, a fifth I/O unit comprising a plurality of sense amplifiers, and a sixth I/O unit comprising a plurality of sense amplifiers. The third bank is preferably located opposite to the first bank on the semiconductor memory device. The fourth bank comprises a seventh block of memory cells, an eighth block of memory cells, a seventh I/O unit comprising a plurality of sense amplifiers and an eighth I/O unit comprising a plurality of sense amplifiers. The fourth bank is preferably located opposite to the second bank on the semiconductor memory device.
In another aspect, the circuits comprise a first and second circuit. The first circuit comprises a plurality of multiplexers, and is operatively connected to the first pad group and to the first, third, fifth and seventh I/O units, respectively, via a first data bus, a third data bus, a fifth data bus and a seventh data bus. The second circuit comprises a plurality of multiplexers, and is operatively connected to the second pad group and to the second, fourth, sixth and eighth I/O units, respectively, via a second data bus, a fourth data bus, a sixth data bus and an eighth data bus.
Preferably, the banks and circuits are disposed on the semiconductor device such that all of the data paths between the banks and the circuits are substantially the same length. Further, the data paths are preferably substantially the same width. Further, the data buses connecting the pad groups and circuits are preferably substantially the same length and width.
In another aspect of the invention, each of the I/O units comprise a plurality of multiplexers and each of the circuits comprise a plurality of sense amplifiers.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 6072744 (2000-06-01), Kwean
patent: 6091620 (2000-07-01), Kablanian
patent: 6163475 (2000-12-01), Proebsting
patent: 10241363 (1998-11-01), None
Matsumiya Et Al., A 15-ns 16-Mb SRAM with Interdigitated Bit-Line Architecture, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1497-1503.

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