Semiconductor memory apparatus with a spare memory cell array

Details Semiconductor memory apparatus with a spare memory cell array Semiconductor memory apparatus with a spare memory cell array

1990-07-26

1992-05-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

051133717

ABSTRACT:
In a test of a fabricated semiconductor memory chip, a test control signal is supplied to a test control circuit, so that a spare memory cell array is tested whether spare memory cells are functionable for writing and reading of data. The test control signal is applied to terminals which are used for the supplying of an address signal, etc. For this purpose, the test control signal has a level different from that of the address signal. Therefore, the spare memory cell array can be tested simultaneously with a test of normal memory cell array.

REFERENCES:
patent: 4567580 (1986-01-01), Varshney
patent: 4860260 (1989-08-01), Saito et al.

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