Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2002-01-15
2004-01-13
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06678187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory apparatus using tunnel magnetic resistance elements as memory cells. Hereinafter, the tunnel magnetic resistance element is referred to as TMR element or simply cell. In addition, the semiconductor memory apparatus using the TMR elements is referred to as MRAM.
2. Description of the Prior Art
FIG. 1
shows the theory of an TMR element. The TMR element is composed of a free magnetic substance layer
901
, a tunnel insulation film
902
, and a pin magnetic substance layer
903
that are successively disposed. The amount of a current that flows in the tunnel insulation film
902
varies depending on the orientation of the magnetization of the free magnetic substance layer
901
. A larger current or a smaller current is assigned “1” whereas the other current is assigned “0”. The orientation of the pin magnetic substance layer
903
has been fixed from the time the device was produced.
With reference to
FIGS. 2 and 3A
, when data is written to a selected cell
913
, a current
911
C and a current
912
C are caused to flow in a selected word line
911
and a selected bit line
912
, respectively. At that point, a magnetic field denoted by an arrow mark
931
is applied to the selected cell
913
. A magnetic field denoted by an arrow
932
is applied to cells
914
connected to the selected word line
921
other than the cell
913
. A magnetic field denoted by an arrow
933
is applied to cells
915
connected to the selected bit line
922
other than the cell
913
. A magnetic substance (for example, NiFe) that has asteroid characteristic in which the orientation of the magnetization is easily reversed with a magnetic field applied in a diagonal direction as shown in
FIG. 3A
is used as the cells. In
FIG. 3A
, a diamond shape
934
represents the intensity of the magnetic field with which the orientation of the magnetization of the magnetic substance is reversed. Thus, only the selected cell
913
is magnetized in a desired orientation.
FIG. 4
is a schematic diagram showing an MRAM disclosed in U.S. Pat. No. 5,640,343 (hereinafter referred to as first related art reference).
Referring to
FIG. 4
, a diode
941
is connected to a TMR element
942
in series. The TMR element
942
is denoted by a symbol of a resistor, because the resistance when the value of data written to the TMR element
942
is “1” is different from the resistance when the value of data written thereto is “0”, As shown in
FIG. 4
, a tunnel current flows in only a selected cell
943
. By comparing the current with a reference current, the orientation of the magnetization of the cell (namely, the cell data) is determined.
FIG. 5
is a schematic diagram showing the concept of an MRAM disclosed in Applied Physics Letters Vol. 77, Num. 13, Sep. 25, 2000 (hereinafter referred to as second related art reference). The MRAM as the second related art reference does not have diodes. Lines other than a selected word line and a selected bit line are grounded. A current is caused to flow in only the selected word line and the selected bit line.
In the first related art reference, since a diode must be connected to a magnetic substance in series, the number of production steps increases. Thus, the production cost rises.
In addition, in the first related art reference, it is necessary to apply two types of voltage to each bit line and each word line. On the other hand, in the second related art reference, it is necessary to apply two types of voltage to each word line. Thus, the structure of a switch for selecting the voltages becomes complicated.
Moreover, in the second related art reference, since non-selected lines are fixed to a ground line of the chip. Thus, noise of the ground line adversely affects a signal. In other words, when there is an alternate noise voltage between a ground line of a sense amplifier and a ground line connected to a non-selected line, an alternate noise current flows in the sense amplifier.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an MRAM that needs not a process for forming diodes, thereby allowing the chip size to be decreased and the production cost to be reduced.
Another object of the present invention is to provide an MRAM that prevents the areas of the selectors and sense amplifiers of the chip from increasing, thereby allowing the chip size to be decreased and the production cost to be lowered.
A further object of the present invention is to provide an MRAM that prevents a noise current due to ground noise from flowing in an input portion of a sensor amplifier, thereby preventing a read error from taking place.
According to the present invention, there is provided a semiconductor memory apparatus using tunnel magnetic resistance elements, the apparatus comprising: a plurality of cell arrays, each of the cell arrays having a plurality of word lines, a plurality of bit lines each of which intersects with the plurality of word lines, and a plurality of tunnel magnetic resistance elements connected between respective word lines and respective bit lines at the intersections thereof; means, when data is read, for connecting a read word line, which is a word line connected to a tunnel magnetic resistance element from which the data is read, to a voltage source of a first voltage; means, when the data is read, for connecting a read bit line, which is a bit line connected to the tunnel magnetic resistance element from which data is read, to an input of a sense amplifier having an input voltage that is a second voltage that is different from the first voltage; means, when the data is read, for causing word lines, except for the read word line, in a first cell array that contains the tunnel magnetic resistance element from which data is read to be in a floating state; and means, when the data is read, for causing bit lines, except for the read bit line, in the first cell array to be in a floating state.
The semiconductor memory apparatus may further comprise: a subtracter for subtracting an offset current from a current that flows to or from the sense amplifier when the data is read.
In the semiconductor memory apparatus, the offset current may flow in a dummy cell.
In the semiconductor memory apparatus, the dummy cell is included in a second cell array that is different from the first cell array.
In the semiconductor memory apparatus, the second cell array may be a cell array dedicated for generating the offset current.
In the semiconductor memory apparatus, in the second cell array, tunnel magnetic resistance elements to which “0” has been written and tunnel magnetic resistance elements to which “1” has been written may be arranged in a checker shape.
In the semiconductor memory apparatus, in the second cell array, tunnel magnetic resistance elements to which “0” has been written and tunnel magnetic resistance elements to which “1” has been written may be arranged in a stripe pattern.
In the semiconductor memory apparatus, in the second cell array, the difference between the number of tunnel magnetic resistance elements to which “0” has been written and the number of tunnel magnetic resistance elements to which “1” has been written may be 1 or less.
In the semiconductor memory apparatus, the second cell array may be a cell array that contains a tunnel magnetic resistance element from and to which data is read and written.
In the semiconductor memory apparatus, the second cell array may have a dummy word line and a dummy bit line, and a current that flows in the dummy bit line may be used as the offset current when the dummy word line is connected to the voltage source of the first voltage, the dummy bit line is connected to the subtracter, word lines that are contained in the second cell array and that are not the dummy word line are caused to be in a floating state, and bit lines that are contained in the second cell array and that are not the dummy bit line are caused to be in a floating state.
In the semiconductor memory apparatus, the difference betwee
Honda Takeshi
Sakimura Noboru
Sugibayashi Tadahiko
Elms Richard
NEC Corporation
Nguyen Nam
Scully Scott Murphy & Presser
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