Semiconductor memory apparatus including synchronous delay...

Static information storage and retrieval – Read/write circuit – Particular write circuit

Reexamination Certificate

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Details

C365S193000, C365S194000, C365S233100

Reexamination Certificate

active

07656722

ABSTRACT:
A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver.

REFERENCES:
patent: 6807108 (2004-10-01), Maruyama et al.
patent: 6836165 (2004-12-01), Goto et al.
patent: 6982923 (2006-01-01), Ootsuki
patent: 7088625 (2006-08-01), Merritt et al.
patent: 2005/0254307 (2005-11-01), Dietrich et al.
patent: 2007/0073982 (2007-03-01), Kim et al.
patent: 2008/0002491 (2008-01-01), Ku et al.
patent: 10-0080510 (1994-12-01), None
patent: 100154724 (1998-07-01), None
patent: 1020030002228 (2003-01-01), None
patent: 1020060027057 (2008-03-01), None
patent: WO-00/13184 (2000-03-01), None

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