Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-03-28
2006-03-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
07020033
ABSTRACT:
A memory unit includes unit blocks laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells laid out to form a cell matrix and redundant lines including redundant memory cells each used for repairing an abnormal memory cell. Every plurality of unit blocks forms a two-dimensional group oriented in a first direction and a second direction, and the redundant lines connected in the first and second directions are shared by the unit blocks pertaining to the two-dimensional group. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs in storage means provided for each of the unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell and, then, finds a redundant line to be used for repairing an abnormal memory cell for each of the unit blocks pertaining to the two-dimensional group on the basis of the address pairs stored in the storage means.
REFERENCES:
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patent: 2004/0208070 (2004-10-01), Nagata et al.
patent: 2005/0007841 (2005-01-01), Nagata et al.
patent: 07-146340 (1995-06-01), None
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Kodama Hiroaki
Nagata Kou
Elms Richard
Kananen Ronald P.
Nguyen Hien
Sony Corporation
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