Semiconductor memory apparatus and method of controlling the...

Details Semiconductor memory apparatus and method of controlling the... Semiconductor memory apparatus and method of controlling the...

2007-06-29

2009-10-13

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S191000, C365S222000, C365S230060

Reexamination Certificate

active

07602661

ABSTRACT:
A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether general cells corresponding to input addresses are repaired or not and activate the redundant cells, decoding units configured to decode a refresh address or a normal address and activate the general cells or the redundant cells according to the decoded refresh address or normal address, and a control unit configured to perform control such that the addresses, which are output by the decoding units, are not input to the repair sets according to a control signal.

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