Static information storage and retrieval – Systems using particular element – Amorphous
Reexamination Certificate
2008-07-08
2008-07-08
Le, Vu A (Department: 2824)
Static information storage and retrieval
Systems using particular element
Amorphous
C365S148000
Reexamination Certificate
active
11409097
ABSTRACT:
A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1is again turned on to write reset in the cell MC0.
REFERENCES:
patent: 6879513 (2005-04-01), Ooishi
patent: 6954385 (2005-10-01), Casper et al.
patent: 2001-210073 (2001-08-01), None
Woo Yeong Cho, et al. “A 1.18 μm 3.0V 64Mb Non-Volatile Phase-Transition Random-Access Memory (PRAM)”, 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004/Session 2/Non-Volatile Memory/2.1, Feb. 16, 2004.
Kajigaya Kazuhiko
Nakai Kiyoshi
Elpida Memory Inc.
Le Vu A
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