Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reissue Patent
2011-08-23
2011-08-23
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S170000, C365S185010
Reissue Patent
active
RE042648
ABSTRACT:
A source block (B0) and the logical page number (“8”) of a write target page are identified from the logical address of the write target page. Data objects (DN8, DN9, . . . , DN12) to be written, which a host stores in a page buffer (2), are written into the data areas (DA) of the pages (Q0, Q1, . . . , Q4) of a destination block (Bn), starting from the top page (Q0) in sequence. The logical page number (“8”) of the write target page is written into the redundant area (RA) of the top page (Q0). The physical page number (“6=8−2”) of the write target page is identified, based on the logical page number (“8”) of the write target page and the page offset (“2”) of the source block (B0). When notified by the host of the end of the sending of the data objects (DN8, . . . , DN12), the data items (D13, . . . , D31, D0, D1, . . . , D7) in the source block (B0) are transferred to the pages (Q5, Q6, . . . , Q31) in the destination block (Bn) via the page buffer (2) sequentially and cyclically, starting from the page (P11) situated cyclically behind the write target page (P6) by the number (“5”) of pages of the data objects (DN8, . . . , DN12).
REFERENCES:
patent: 5519847 (1996-05-01), Fandrich et al.
patent: 5579502 (1996-11-01), Konishi et al.
patent: 5611067 (1997-03-01), Okamoto et al.
patent: 5745912 (1998-04-01), Konishi et al.
patent: 5963983 (1999-10-01), Sakakura et al.
patent: 6141726 (2000-10-01), Dell
patent: 6721843 (2004-04-01), Estakhri
patent: 6763424 (2004-07-01), Conley
patent: 6938116 (2005-08-01), Kim et al.
patent: 6965963 (2005-11-01), Nakanishi et al.
patent: 2003/0204675 (2003-10-01), Dover et al.
patent: 1134662 (2001-09-01), None
patent: 5-046461 (1993-02-01), None
patent: 5-313989 (1993-11-01), None
patent: 9-282111 (1997-10-01), None
patent: 09282111 (1997-10-01), None
patent: 11-203885 (1999-07-01), None
patent: 98/43248 (1998-10-01), None
English language Abstract of JP 5-046641.
English language Abstract of JP 5-313989.
English language Abstract of JP 11-203885.
English language Abstract of JP 9-282111.
Wu et al., “eNVy: A Non-Volatile, Main Memory Stotage System,” ACM Sigplan Notices, ACM, Association for Computing Machinery, New York, NY, US, vol. 29, No. 11, Nov. 1, 1994, pp. 86-97, XP000491727, ISSN: 0362-1340.
Chiang et al., “Managing flash memory in personal communication devices,” Consumer Electronics, 1997, ISCE '97, Proceedings of 1997 IEEE International Symposium on Singapore Dec. 2-4, 1997, New York, NY, USA, IEEE, US, Dec. 2, 1997, pp. 177-182, XP010268685, ISBN: 0-7803-4371-9.
Honda Toshiyuki
Inagaki Yoshihisa
Bradley Matthew
Ellis Kevin L
Greenblum & Bernstein P.L.C.
Panasonic Corporation
LandOfFree
Semiconductor memory apparatus and method for writing data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory apparatus and method for writing data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory apparatus and method for writing data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2714458