Semiconductor memory apparatus and activation signal...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S205000, C365S207000, C365S210130

Reexamination Certificate

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07035149

ABSTRACT:
A semiconductor memory apparatus, comprising a cell array comprising a plurality of memory cells; a sense amplifier; and a self-timing unit comprising a plurality of dummy bit-lines, selecting the dummy bit-line based on the position of the memory cell of which a data is read out, and generating an activation signal for controlling an activation timing of a sense amplifier at a time of reading data.

REFERENCES:
patent: 6490214 (2002-12-01), Kawasumi
patent: 6717877 (2004-04-01), Suzuki et al.
patent: 2004/0095824 (2004-05-01), Kurumada et al.
patent: 2005/0073885 (2005-04-01), Suzuki et al.
patent: 2002-216481 (2002-08-01), None

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