Semiconductor memory apparatus

Details Semiconductor memory apparatus Semiconductor memory apparatus

2007-03-06

2009-02-17

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S195000

Reexamination Certificate

active

07492651

ABSTRACT:
A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.

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