Static information storage and retrieval – Read/write circuit – Testing
Patent
1993-05-24
1994-12-13
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
36518907, 365193, G11C 700
Patent
active
053734726
ABSTRACT:
A semiconductor memory apparatus of the present invention comprises a semiconductor memory circuit and a test mode control circuit, the test mode control circuit sets a source voltage to a second voltage, which is larger than a first voltage used at the time of the normal operation, and controls the semiconductor memory circuit to be set to a predetermined voltage stress test mode by inputting a combination clock signal of clock signals unused at the time of the normal operation.
REFERENCES:
patent: 5119337 (1992-06-01), Shimizu et al.
patent: 5245577 (1993-09-01), Duesman et al.
patent: 5255229 (1993-10-01), Tanaka et al.
Kabushiki Kaisha Toshiba
Popek Joseph A.
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