Semiconductor memory and test method for the same

Details Semiconductor memory and test method for the same Semiconductor memory and test method for the same

2007-07-17

2008-12-30

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S230050

Reexamination Certificate

active

07471579

ABSTRACT:
In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspondingly to each complementary sub bit line between the complementary sub bit line and a complementary main bit line corresponding to the complementary sub bit line. Furthermore, the semiconductor memory includes a hierarchical switch control unit for turning off all the sub bit line hierarchical switch and the complementary sub bit line hierarchical switch when a given signal is input.

REFERENCES:
patent: 5610871 (1997-03-01), Hidaka
patent: 5612919 (1997-03-01), Arimoto
patent: 5701269 (1997-12-01), Fujii
patent: 5748538 (1998-05-01), Lee et al.
patent: 6327202 (2001-12-01), Roohparvar
patent: 8-195100 (1996-07-01), None

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