Semiconductor memory and screening test method thereof

Details Semiconductor memory and screening test method thereof Semiconductor memory and screening test method thereof

1992-11-19

1994-12-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365206, 36518909, G11C 700

Patent

active

053771524

ABSTRACT:
A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

REFERENCES:
patent: 4853897 (1989-08-01), Nogami et al.
patent: 4907200 (1990-03-01), Ikawa et al.
patent: 5255235 (1993-10-01), Miyatake

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