Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2003-02-10
2004-08-17
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S233500
Reexamination Certificate
active
06778448
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and an output signal control method and circuit in the semiconductor memory and, more particularly, to a semiconductor memory and an output signal control method and circuit in the semiconductor memory that are preferably used to prevent generation of output noise in the semiconductor memory.
2. Description of the Related Art
In a data read, a semiconductor memory including a nonvolatile semiconductor memory generally amplifies a small current flowing from a memory cell by a sense amplifier, and outputs data stored in the memory cell as an “H”- or “L”-level electrical signal through an output buffer.
FIG. 1
is a block diagram showing the first prior art of an output control circuit for controlling transfer of a signal output from a sense amplifier to an output buffer. As shown in
FIG. 1
, a signal output via a sense amplifier
1
through a bit line connected to a memory cell is supplied via a switching transistor
2
to a latch circuit
5
which is made up of inverters
3
and
4
and constitutes output latch unit.
The signal latched by the latch circuit
5
is supplied as data DATA to an output buffer
6
. When the output buffer
6
is in an enable state, the data DATA is output as an output signal OUT through a CMOS inverter
7
made up of a p-channel transistor and n-channel transistor.
An output control signal /OE which is externally input via a control signal input terminal /OE_pin is supplied as an output buffer control signal OEB to the output buffer
6
via a control input buffer
11
. When this output buffer control signal OEB is at “L” level, the output buffer
6
is in an enable state.
The operation of the conventional output signal control circuit having this arrangement will be described with reference to the timing chart of FIG.
2
.
When an address AD changes, as shown in
FIG. 2
, this change is detected by an address change detection circuit (not shown), an address change detection signal ATD changes to “H” level for a predetermined period, and an output from a cell corresponding to the new address connected to a bit line is sensed. When the address change detection signal ATD changes to “H” level, a sense amplifier operation signal PD supplied to the sense amplifier
1
changes from “H” level to “L” level, and the sense amplifier
1
performs data sense operation.
When the address change detection signal ATD changes to “L” level, the address change detection circuit outputs a sense data reception signal LT and supplies it to the switching transistor
2
. At this time, the sense amplifier operation signal PD changes to “H” level.
Upon receiving the sense data reception signal LT, the switching transistor
2
is turned on. The sense data DATA of the sense amplifier
1
is latched by the latch circuit
5
and supplied to the output buffer
6
. The sense data DATA supplied to the output buffer
6
is output to the outside as the output signal OUT via the CMOS inverter
7
.
As described above, the output buffer
6
is in an enable state when the output buffer control signal OEB supplied to its control input terminal is at “L” logic level.
The output buffer control signal OEB supplied to the output buffer
6
is in phase with the output control signal /OE which is externally input via the control signal input terminal /OE_pin. Hence, as shown in
FIG. 2
, the output buffer
6
changes to an enable state during data sense operation of the sense amplifier
1
(“H”-level period of the address change detection signal ATD) depending on the timing at which the output control signal /OE is externally supplied.
In this output signal control circuit, a transistor constituting the output buffer
6
has a high driving capability in order to drive an external load. If the level of the output signal OUT is inverted, the power supply potential varies. If the output signal OUT is inverted during data sense operation of the sense amplifier
1
to vary the power supply potential, large output noise is generated to destroy sense data owing to the malfunction of the sense amplifier
1
or the like. As a result, erroneous data is undesirably latched by the latch circuit
5
.
In a flash memory for performing automatic algorithm operation of a write/erase, data to be output to the output buffer is switched from polling data to read data by switching the address from a given block to another block in a suspend read performed during automatic algorithm operation. At this time, if polling data and read data are switched during data sense operation of the sense amplifier
1
, output noise is generated by variations in power supply potential.
FIG. 3
is a block diagram showing the second prior art, and shows the arrangement of an output signal control circuit in a flash memory. In
FIG. 3
, the same reference numerals as in
FIG. 1
denote the same parts as in
FIG. 1
, and a detailed description thereof will be omitted.
In the circuit of
FIG. 3
, a second switching transistor
70
is interposed between a latch circuit
5
and an output buffer
6
. Polling data is supplied between the second switching transistor
70
and output buffer
6
via a transistor
68
. An operation switching signal POLL is supplied to the gate of the transistor
68
, whereas the inverted signal of the operation switching signal POLL is supplied to the gate of the second switching transistor
70
via the inverter
69
.
In the circuit of
FIG. 3
having this arrangement, while the address change detection signal ATD is at “H” level, the operation switching signal POLL falls to “L” level during data sense amplifier of a sense amplifier
1
, as shown in the timing chart of FIG.
4
. Then, the transistor
68
is turned off to stop outputting polling data. The transistor
70
is turned on to supply an output from the sense amplifier
1
to the output buffer
6
. Similarly to the first prior art, the output signal OUT is inverted during data sense operation of the sense amplifier
1
, and the power supply potential varies to generate output noise. Consequently, erroneous data is undesirably latched.
In any case, in the conventional circuit, if the level of the output signal OUT from the output buffer
6
varies during sense operation of the sense amplifier
1
, output noise generated by variations in power supply voltage destroys the sense data DATA of the sense amplifier
1
.
To prevent the malfunction of the sense amplifier
1
under the influence of the above-described output noise, the techniques disclosed in Japanese Patent Application Laid-Open Nos. 54681/1993, 63970/1996, and 173387/1989 have conventionally been proposed.
In a “semiconductor memory” disclosed in Japanese Patent Application Laid-Open No. 54681/1993, a transistor which is set off for a predetermined time corresponding to an address change is interposed between the power supply and the output point of a sense amplifier circuit. In switching the address, the output level of the sense amplifier circuit is reduced to prevent output of erroneous data even if a memory cell is erroneously selected.
In a “semiconductor memory” disclosed in Japanese Patent Application Laid-Open No. 63970/1996, when output data from a sense amplifier changes, an output from the sense amplifier is disabled before an output from an output buffer is inverted. After the output from the sense amplifier is stabilized, the output from the output buffer is inverted. Variations in power supply potential by inversion operation of the output buffer hardly influences the operation of the sense amplifier. This prevents the malfunction of the sense amplifier under the influence of inversion operation of the output buffer.
In a “semiconductor integrated circuit” disclosed in Japanese Patent Application Laid-Open No. 173387/1989, the output time of data from a sense amplifier to an output buffer is set short until a memory cell is newly selected to output data from the output buffer after the address changes. After that, the output time is set long. This prevents output of erroneou
Arent & Fox PLLC
Fujitsu Limited
Ho Hoai
LandOfFree
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