Semiconductor memory and method of saving energy of the memory

Details Semiconductor memory and method of saving energy of the memory Semiconductor memory and method of saving energy of the memory

2001-03-28

2002-05-07

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Complementing/balancing

C365S203000

Reexamination Certificate

active

06385105

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memories such as dynamic or static random across memories, and more specifically to a power saving semiconductor memory and a method of saving the energy consumption of a semiconductor memory.
2. Description of the Related Art
In a prior art semiconductor memory, shown in
FIG. 1
, a plurality of bit-line pairs
5
are provided on a memory cell array
1
extending from a near side of the array to a far side of the array with respect to write and read amplifiers
8
and
9
. Memory cells of the array are connected to associated bit-line pairs. For high speed operation of the memory, a near-end balancer
2
i
(where i=1, . . . , N) is connected to the near end of a corresponding bit-line pair (or I/O bus)
5
and a far-end balancer
3
i
is connected to the far end of the corresponding bit-line pair. A plurality of such near-end balancers
2
are respectively connected to prechargers
4
i
. A clock source
6
supplies clock pulses to a control driver
7
which in turn drives both far-end balancers
2
and near-end balancers
3
. During a write mode (FIG.
2
), data is amplified by the write amplifiers
8
and write clock pulses are supplied to the near-end and far-end balancers
2
and
3
through the control driver
7
. When a write clock pulse is low, all bit lines of the memory cells are pre-charged and voltages developed on the bit lines of each pair are balanced with each other by the associated near-end balancer
2
and far-end balancer
3
. When the write clock pulse raises to high level, the outputs of the write amplifiers
8
are sent to all bit lines, amplified by sense amplifiers on the cell array and then stored into memory cells that are selected. When the write clock pulse goes low again, the process is repeated for the next cycle of pre-charging and balancing write operation. In a similar manner, read clock pulses are supplied during a read mode to the near-end and far-end balancers
2
and
3
through the control driver
7
so that, when a read clock pulse is low, all bit lines of the memory cells are pre-charged and balanced by all balancers. When the read clock pulse raises to high level, memory cells are selected and data stored in the selected memory cells are read out onto the associated bit-line pairs and amplified by sense amplifiers on the array. The amplified data are extracted from the memory cell array
1
and applied to the read amplifiers
9
associated with the selected memory cells for amplification. When the read clock pulse goes low again, the process is repeated for the next cycle of pre-charging and balancing read operation.
However, the pre-charging and balancing operation are performed during both read and write modes, the consumption of energy is significant and hence it is desired to provide a memory cell array that can operate with less energy.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory that can save energy.
According to one aspect, the present invention provides a semiconductor memory comprising an array of memory cells, a plurality of bit-line pairs to which the memory cells of the array are connected, and a plurality of prechargers respectively connected to the bit-line pairs. The prechargers are active during a read mode of the memory and remain inactive during a write mode of the memory.
The semiconductor memory may include a first plurality of balancers connected respectively to first ends of the bit-line pairs and a second plurality of balancers connected respectively to second, opposite ends of the bit-line pairs. The first plurality balancers are active during the read and write modes and the second plurality of balancers are active during the read mode and remain inactive during the write mode. Each of the prechargers may further include a balancing transistor connected across the bit lines of a corresponding pair, the balancing transistor being active at least during the write mode.


REFERENCES:
patent: 5369620 (1994-11-01), Sugibayashi
patent: 5701268 (1997-12-01), Lee et al.
patent: 5875139 (1999-02-01), Semi
patent: 5903502 (1999-05-01), Porter
patent: 6023437 (2000-02-01), Lee
patent: 6069828 (2000-05-01), Kaneko et al.

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