Semiconductor memory and method of operating the same

Details Semiconductor memory and method of operating the same Semiconductor memory and method of operating the same

2001-09-28

2003-07-29

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S189011, C365S233100

Reexamination Certificate

active

06600688

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory including a sense amplifier and, more particularly, to a technology for securely reading out data which is written in a memory cell.
2. Description of the Related Art
In a semiconductor memory such as DRAM, data (charge) which is written in a memory cell leaks in a substrate and the like and disappears over time. Hence, the DRAM, for example, carries out refresh operation by rewriting the data in the memory cell at regular intervals in order to compensate a decrease in an amount of the charge in the memory cell.
In the DRAM, read operation and writing operation are generally carried out by using two bit lines (bit line pair). In the read operation, for example, reference voltage is first supplied to the bit line pair (precharge operation). Next, the data (storage charge) which is held in the memory cell is transmitted to one bit line. The storage charge in the memory cell is shared according to an amount ratio between the memory cell and the bit line, whereby voltage of one bit line changes. The voltage is compared with voltage of the other bit line (reference voltage), and “H data” or “L data” is read out.
Supposing that a state in which the charge is accumulated in the memory cell is “H state” and a state in which the charge is extracted from the memory cell is “L state”, the memory cell in the H state changes to the L state over time, as described above. For this reason, a difference between the voltage of one bit line to which the charge in the H state is transmitted and the voltage of the other bit line (reference voltage) decreases as time passes. Meanwhile, the voltage of one bit line to which the charge in the L state is transmitted is grounding voltage in general, and hence a difference between this voltage and the voltage of the other bit line (reference voltage) does not change even after the passage of time. Therefore, a read margin in the H state is smaller than a read margin in the L state. In other words, the memory cell in the H state is difficult to read out as compared with the memory cell in the L state.
Recently, a sense amplifier with improved read margin in the H state has been developed in order to eliminate the disadvantage like the above. In this sense amplifier, the voltage of one of the bit lines out of the bit line pair is forced to change by using a coupling capacitance which is connected to the bit line, immediately before the accumulated charge of the memory cell is transmitted to the bit line.
Since operating voltage of the semiconductor memory such as the DRAM has been decreased, it has been difficult to keep an enough voltage difference between the bit line pair and to operate the sense amplifier without fail. For this reason, a method of increasing the voltage difference between the bit line pair in the read operation by using the coupling capacitance which is connected to the bit line is indispensable to the recent DRAM.
FIG. 1
shows a principle part of DRAM to which this kind of sense amplifier is applied.
A sense amplifier
10
is connected to a bit line pair BLT, BLC. The bit line pair BLT, BLC are connected to memory cell arrays
14
via isolation gates
12
. The isolation gates
12
on the left side of the drawing are controlled by a bit line control signal BTLP. The isolation gates
12
on the right side of the drawing are controlled by a bit line control signal BTRP. In the read/write operation, one of the memory cell arrays
14
on both sides of the drawing is connected to the sense amplifier
10
by the bit line control signals BTLP, BTRP.
The memory cell array
14
includes a plurality of memory cells MC. Each of the memory cells MC consists of a capacitor for storing the data and a transfer transistor for connecting the capacitor to the bit line BLT (or BLC). In this example, a gate of the transfer transistor of the memory cell MC which is connected to the bit line BLT receives a word line signal WLT. A gate of the transfer transistor of the memory cell MC which is connected to the bit line BLC receives a word line signal WLC.
The sense amplifier
10
includes a latch
10
a,
capacitances
10
b,
10
c
made of nMOS transistors, write switches
10
d,
10
e
and read switches
10
f,
10
g.
The latch
10
a
consists of two of CMOS inverters with these inputs and outputs connected to each other. The latch
10
a
is activated or inactivated according to a sense amplifier activating signal which is not shown. A source and a drain of the capacitance
10
b
are connected to the bit line BLT and a control signal BLPLTN is received at its gate. A source and a drain of the capacitance
10
c
are connected to the bit line BLC and a control signal BLPLCN is received at its gate.
Either source or drain of the write switch
10
d
is connected to the bit line BLT and the other of the source or drain is connected to an input/output node ND
01
(data bus). A write control signal WSELP is received at its gate. Either source or drain of the write switch
10
e
is connected to the bit line BLC and the other of the source or drain is connected to an input/output node ND
02
(data bus). The write control signal WSELP is received at its gate.
Either source or drain of the read switch
10
f
receives a read control signal RDRVN, the other of the source or drain is connected to an input/output node ND
03
(data bus) and its gate is connected to the bit line BLT. Either source or drain of the read switch
10
g
receives the read control signal RDRVN, the other of the source or drain is connected to an input/output node ND
04
(data bus) and its gate is directly connected to the bit line BLC.
In the sense amplifier
10
, currents passing through the read switches
10
f
,
10
g
vary according to the voltage difference between the bit line pair BLT, BLC. Voltages (amplification voltage) are generated in the input/output nodes ND
03
, ND
04
according to the difference of the current, and the generated voltage is transmitted to a read amplifier and the like. Namely, the read switch
10
f
(or
10
g
) has a function of amplifying read data which is transmitted to the bit line BLT (or BLC). This kind of circuit system is generally referred to as a direct sense system. The sense amplifier of the direct sense system does not connect the bit lines BLT, BLC and column switches
16
c
,
16
d
directly. For this reason, the voltages of the bit lines BLT, BLC do not change by the operations of the column switches
16
c
,
16
d
. That is, even when a column selecting signal is activated before the data which are transmitted from the memory cell MC to the bit lines BLT, BLC are fully amplified, the read operation is carried out properly. Therefore, it is suitable for high speed operation.
The input/output node ND
01
is connected to a write data line WDT via a column switch
16
a
. The input/output node ND
02
is connected to a write data line WDC via a column switch
16
b.
The input/output node ND
03
is connected to a read data line RDT via the column switch
16
c
. The input/output node ND
04
is connected to a read data line RDC via the column switch
16
d
. Gates of the column switches
16
a
to
16
d
receive a column selecting signal CSLP. The write data lines WDT, WDC are connected to a write amplifier (not shown) which receives write data from input/output terminals. The read data lines RDT, RDC are connected to a read amplifier (not shown) which outputs read data to the input/output terminals.
FIG. 2
shows an example of the operation of the aforementioned sense amplifier
10
. In this example, the read data or the write data is transmitted to the bit line BLT. The bit line BLC (reference) acts as a line for supplying the reference voltage.
(A) Read Cycle
First, the memory cell array
14
on the left side of
FIG. 1
is selected according to the supply of a row address signal, and the bit line control signal BTRP is inactivated (low level) (FIG.
2
(
a
)). The not-shown bit line control signal BTRP is activated, and the memory cell array
14
and t

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