Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1996-05-03
1998-09-15
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523006, G11C 700
Patent
active
058089438
ABSTRACT:
A semiconductor memory, such as Dynamic Random Access Memory (DRAM), is provided for replacing a defective memory cell with a spare memory cell. The DRAM includes a main section which has a memory cell array with a plurality of memory cells arranged in an array. A spare section having a spare memory cell array also includes a plurality of memory cells arranged in an array. An address decoder specifies addresses, respectively, of the main section array and the spare section array. A defective bit replacement control circuit is connected to the address decoder and includes a plurality of electrically rewritable nonvolatile memory cells. The address decoder conducts a change-over operation for specifying an address of the first or second arrays according to a storage state, i.e., contents, of electrically rewritable nonvolatile memory cells.
REFERENCES:
patent: 5233566 (1993-08-01), Imamiya et al.
patent: 5315551 (1994-05-01), Hirayama
Amano Shigeki
Sato Yasuo
Nippon Steel Corporation
Popek Joseph A.
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