Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-19
2001-03-06
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000
Reexamination Certificate
active
06198122
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method of fabricating the same.
In fabricating reliable semiconductor memories such as DRAMs, it is required to, e.g., decrease the resistance of a capacitor electrode or an interconnection, reduce the fabrication steps to provide inexpensive devices, and planarize the surface in each step, particularly, in a lithography step to widen the process margin for lithography.
One conventional method of fabricating a DRAM having a stacked capacitor is to form an interconnection such as a bit line, form a contact for connecting the storage node electrode of a capacitor and form the storage node electrode, form a capacitor insulating film and a plate electrode, and form an upper interconnection (e.g., IEDM
95
-907).
When the fabrication method as described above is used, however, although the resistance of the capacitor electrode can be decreased by improving the plate electrode material, planarization when lithography is performed is not realized. Accordingly, it is not easy to fabricate devices, such as 1-Gbit DRAMs, having fine patterns.
Another example of conventional stacked capacitors is described in “P- Y. Lesaicherre et al., “A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO
3
and RIE patterned RuO
2
/TiN storage nodes”, IEDM Technical Digest, pp. 831-834, 1994”.
The technology described in this reference will be briefly described below with reference to
FIGS. 1A
to
1
D.
First, a 600-nm thick thermal oxide film
162
is formed on a silicon substrate
161
, and a contact hole is formed in this thermal oxide film
162
. Subsequently, a polysilicon plug
163
is formed in this contact hole (FIG.
1
A). A TiN film
164
and a 500-nm thick RuO
2
film
165
are formed on the entire surface by sputtering (FIG.
1
B). Next, an island resist mask
166
is formed on the RuO
2
film
165
by using lithography and used as a mask to pattern the RuO
2
film
165
and the TiN film
164
by RIE (FIG.
1
C). After a surface treatment is performed for the RuO
2
film
165
, an SrTiO
3
film
167
is deposited by ECRMOCVD. Finally, a TiN film and an Al film
168
are formed on the entire surface by sputtering to complete an (Al/TiN/SrTiO
3
/RuO
2
/TiN/poly-Si) stacked capacitor including Al as the plate electrode
168
, SrTiO
3
as the capacitor insulating film
167
, and the RuO
2
film as the storage electrode
165
(FIG.
1
D).
The above description relates only to the fabrication steps of the storage node electrode contact and the capacitor. When the above method is applied to an actual DRAM, the steps of forming a MOSFET and a bit line are added to the above steps, and the polysilicon plug is connected to the source or drain of the MOSFET, rather than the silicon substrate.
In the above conventional technology, however, the storage nodes are separated by patterning the storage node conductive film
165
by using the island resist pattern as a mask. Accordingly, the adjacent storage nodes cannot be made closer to each other than the lithography limit. Consequently, the effective storage node area cannot be well increased.
Also, when a plurality of storage nodes
165
are arranged in a matrix manner as shown in
FIG. 2A
in the above conventional technology, if the storage node electrodes
165
and storage node contacts
163
are misaligned as shown in a sectional view of
FIG. 2B
taken along a line
2
B—
2
B in
FIG. 2A
, a capacitor with a structure in which a plate electrode
168
and the storage node contacts
163
oppose each other via a capacitor insulating film
167
is formed. If this is the case, the combination of the materials of the two components can lead to deterioration of the capacitor characteristics, e.g., deterioration of the insulating properties of the capacitor insulating film
167
.
As described above, it is conventionally difficult to perform planarization in lithography and not easy to form fine patterns.
It is also difficult to increase the area of the storage node electrode because the storage nodes cannot be made closer to each other than the lithography limit. Additionally, the capacitor characteristics readily deteriorate due to the misalignment between the storage node electrode and the storage node contact.
BRIEF SUMMARY OF THE INVENTION
It is the first object of the present invention to provide a semiconductor memory which can achieve planarization in the formation of a storage capacitor, and a method of fabricating the same.
It is the second object of the present invention to provide a semiconductor memory which can achieve a wide capacitor area and has improved electrical characteristics and reliability, and a method of fabricating the same.
To achieve the above objects, a semiconductor memory according to the first aspect of the present invention comprises a semiconductor substrate, a memory cell portion formed on the semiconductor substrate and comprising a plurality of stacked capacitors formed on the semiconductor substrate, each of the stacked capacitors having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the semiconductor substrate and comprising a second multilayered interconnecting layer, wherein the plate interconnection includes a portion so formed as to bury the recess and connected to the plate electrode, and the second multilayered interconnecting layer includes an interconnecting layer having an upper surface substantially leveled with an upper surface of the interconnecting layer including the plate interconnection of the first multilayered interconnecting layer.
In the above semiconductor memory, the resistance can be lowered by the interconnecting layers including the plate interconnection. Additionally, the upper surfaces of the interconnecting layers can be substantially leveled with each other in the memory cell region and the peripheral circuit region. As a consequence, planarization can be achieved.
A method of fabricating a semiconductor memory according to the second aspect of the present invention is a method of fabricating a semiconductor memory having a memory cell portion formation region including a capacitor and a peripheral circuit formation region on a semiconductor substrate, comprising the steps of forming, on the semiconductor substrate, an insulating interlayer having a first recess in the memory cell portion formation region and a storage electrode of the capacitor on a bottom surface of the first recess, forming a plate electrode on the storage electrode via a capacitor insulating film, forming a second recess in the insulating interlayer in the peripheral circuit portion, and burying a conductive film in the first and second recesses to simultaneously form interconnecting layers equal in level in the memory cell portion and the peripheral circuit portion.
In the above semiconductor memory fabrication method, the conductor film is simultaneously buried in the first and second recesses. Accordingly, the resistance can be lowered without increasing the number of the fabrication steps. In addition, planarization can be achieved because the heights of the interconnecting layers can be made substantially equal to each other in the region (memory cell region) where the first recess is formed and the region (peripheral circuit region) where the second recess is formed. Consequently, the process margin in lithography can be increased.
In the above fabrication method, it is also possible to form the insulating interlayer by an insulating film X and an insulating film Y formed on this insulating film X and perform the step of forming, on the semiconductor substrate, the insulating interlayer havi
Habu Mariko
Hosotani Keiji
Kohyama Yusuke
Ozaki Toru
Hogan & Hartson LLP.
Kabushiki Kaisha Toshiba
Loke Steven
Tran Thien F.
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