Static information storage and retrieval – Systems using particular element – Negative resistance
Reexamination Certificate
2000-02-25
2001-10-30
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Negative resistance
C305S148000, C305S175000
Reexamination Certificate
active
06310798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and a method for the manufacture thereof, and in particular to a static random access memory (SRAM) using a negative resistance element, and a method for the manufacture thereof.
2. Description of Related Art
The chip area of a semiconductor memory such as SRAM for data storage tends to widen in proportion to the storage capacity thereof. Since widening of the chip area leads to decrease in yield and increase in costs, it is extremely important to reduce the area of a memory cell which is a constituting unit of a memory such as SRAM.
As well as the above-described SRAMs, a large variety of memories such as dynamic random access memories (DRAMs), and electrically erasable programmable read only memories (EEPROMs),are available; however, DRAMs have frequently been used as memories of large capacities. Since the advantages of DRAMs are that a memory cell can be constituted by one capacitor and one transistor, and that the writing speed is high in comparison with EEPROMs, DRAMs have been used most frequently in various electronic applications.
However, DRAMs have a problem that the further shrinkage of the area of memory cells is difficult. The reason is that although data are stored in a DRAM by accumulating electric charge in a capacitor, it is difficult to reduce the size of the capacitor to meet the size reduction required by design standard or design rule in device process design.
In order to solve such a problem, a capacitor utilizing a highly dielectric film, such as BST, has been proposed, but it is still in the study stage, and is not yet practical.
Furthermore, although a system LSI in which a single chip realized system functions which had been performed by a plurality of ICs or LSIs has possibility of increasing the mode using memory cells in system LSIs, such LSIs have a problem of deteriorating the flatness of interlayer insulating films used in the interfaces of the memory cell array and other logic regions interfering with patterning and the like when a DRAM using a stack-type capacitor is used.
On the other hand, since an SRAM, in particular a full complementary metal oxide semiconductor (CMOS) type SRAM has a memory cell structure other than interconnections formed on a substrate, it has less problems of the deterioration of flatness of interlayer insulating films than the above-described DRAM using a stack-type capacitor. However, since a full CMOS-type SRAM has six transistors formed on the substrate: two access transistors, two driver transistors, and two loading transistors, the area of the memory cells is inevitably widened in comparison with a DRAM.
In order to solve the above-described problem of widening of memory cells, an SRAM using a negative resistance has been proposed. Since this type of SRAM is a negative resistance element called a tunneling diode, a high resistance loading element, and an MOS-type transistor element called an access transistor, an SRAM memory cell can be formed only by these three elements. On the other hand, since the tunneling diode is required to have a steep PN junction, it cannot tolerate heat treatment during the CMOS process, and the realization of such an SRAM has been considered to be difficult; however, a method for manufacturing a high-performance tunneling diode by inserting an oxide film between the PN junction of the tunneling diode for controlling the thermal scattering of impurities has recently been proposed. (K. Morita, et al., “High Performance CMOS Compatible Bistable Operation at Extremely Low Supply Voltage by a Novel Si Interband Tunneling Diode,” 56th Annual DEVICE RESEARCH CONFERENCE (DRC), Extended Abstracts, pp. 42-43)
However, the operation of the tunneling diode manufactured by the above-described method has not been reported. Furthermore, in the voltage-current characteristics of the tunneling diode, the ratio of the local maximum value at a low voltage (hereafter referred to as “peak value”) to the local minimum value at a high voltage (hereafter referred to as “valley value”) (hereafter referred to as “peak/valley ratio”) is as small as about 2. Therefore, there has been a problem that an SRAM using such a tunneling diode suffers from the lack of data holding stability.
Since a full CMOS-type SRAM has six transistors formed on a substrate, as described above, there has been a problem of the inevitably widened memory cell area in comparison with the memory cell area of a DRAM. A tunneling diode developed for solving such a problem has a small peak/valley ratio, and there has been a problem of the lack of data holding stability. Furthermore, the above-described tunneling diode has another problem that if the column current of the bit line or the like selecting a memory cell is unnecessarily large, data of the bit selected on reading are broken, and it is difficult to secure stable data read/write characteristics.
SUMMARY OF THE INVENTION
Therefore, in order to solve above-described problems, an object of the present invention is to provide a semiconductor memory with a memory cell area narrowed by elevating bit density per unit area, and a method for manufacturing such a semiconductor memory.
Another object of the present invention is to provide a semiconductor memory that can improve data holding stability even with a tunneling diode having a small peak/valley ratio, and can secure stable data read/write characteristics by controlling the column current, and a method for manufacturing such a semiconductor memory.
According to a first aspect of the present invention, there is provided a semiconductor memory selected by a bit line and a word line comprising: an access transistor whose source-drain region side is connected to the bit line and whose gate side is connected to the word line; a loading resistor connected between the power source and a storage node on the drain region side of the access transistor; and a negative resistor portion connected between ground and the storage node on the drain region side of the access transistor, the negative resistor portion having a tunnel insulating film producing the tunnel effect and formed on the p-type active region with a relatively high impurity concentration, and n-type polysilicon formed in the tunnel insulating film.
According to a second aspect of the present invention, there is provided a semiconductor memory comprising a semiconductor substrate of the first conductivity type; a well of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type; a first active region of the first conductivity type formed on the well of the second conductivity type, and having a relatively high impurity concentration; an access transistor whose source region side is connected to the storage node formed in the first active region; a second active region of the first conductivity type formed on the well of the second conductivity type other than the area of the first active region and the access transistor, and having a relatively high impurity concentration; a storage node direct contact formed on the upper portion of the storage node; a loading resistor connected between the storage node and the power line; a bit-line direct contact formed on the upper portion of the second active region; a bit line formed through the bit-line direct contact; a ground direct contact formed on the upper portion of the first active region; a polysilicon ground wiring formed by forming a polysilicon film on the ground direct contact; a ground contact placed on the polysilicon ground wiring; and a ground line formed on the ground contact, wherein a tunnel insulating film producing the tunneling effect is provided on the bottom portion of the ground direct contact.
According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor memory comprising steps of: arranging an array of active regions isolated by field oxide films on the main surface of a semiconductor substrate o
Mai Son
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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