Semiconductor memory and method for fabricating the same

Semiconductor device manufacturing: process – Forming schottky junction – Using platinum group metal

Reexamination Certificate

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C438S583000, C438S630000, C438S649000, C438S651000, C438S655000, C438S664000, C438S682000, C438S721000, C438S755000

Reexamination Certificate

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06867118

ABSTRACT:
A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor. A silicide layer is formed on the gate electrodes of the memory transistors, the gate electrode of the logic transistor and portions of the top faces, exposed from the sidewall insulating film, of impurity diffusion layers working as source/drain regions of the logic transistor.

REFERENCES:
patent: 6225155 (2001-05-01), Lin et al.
patent: 6333222 (2001-12-01), Kitazawa et al.
patent: 6338993 (2002-01-01), Lien
patent: 6593609 (2003-07-01), Shinkawata
patent: 6624019 (2003-09-01), Kim
patent: 2002-217308 (2002-08-01), None
patent: 2002217308 (2002-08-01), None

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