Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-08-30
2002-09-24
Lam, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06456520
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory including a ferroelectric capacitor and a method for driving the same.
A first known example of a semiconductor memory including a ferroelectric capacitor is composed of, as shown in
FIG. 7
, a field effect transistor (hereinafter referred to as the FET)
1
and a ferroelectric capacitor
2
with a drain region
1
a
of the FET
1
connected to a bit line BL, a source region
1
b
of the FET
1
connected to an upper electrode of the ferroelectric capacitor
2
and a gate electrode
1
c
of the FET
1
connected to a word line WL.
The semiconductor memory of the first conventional example employs the destructive read-out system in which a recorded data is erased in reading the data. Therefore, it is necessary to carry out a rewrite operation after a data read operation, and hence, an operation for reversing the polarization direction of the ferroelectric film (polarization reversing operation) should be carried out after every data read operation.
Since a phenomenon designated as polarization fatigue occurs in a ferroelectric film, the polarizing characteristic of the ferroelectric film is largely degraded when the polarization reversing operation is repeatedly carried out.
As a countermeasure, a semiconductor memory of a second conventional example as shown in
FIG. 8
has been proposed. Specifically, the semiconductor memory of the second conventional example employs the non-destructive read-out system in which a lower electrode
2
b
of a ferroelectric capacitor
2
is connected to a gate electrode
1
c of an FET
1
so as to use the ferroelectric capacitor
2
for controlling the gate potential of an FET
1
. In
FIG. 8
, a reference numeral
3
denotes a substrate.
In writing a data in the semiconductor memory of the second conventional example, a writing voltage is applied between an upper electrode
2
a
of the ferroelectric capacitor
2
working as the control gate and the substrate
3
.
For example, when a data is written by applying a voltage (control voltage) positive with respect to the substrate
3
to the upper electrode
2
a
, downward polarization is caused in a ferroelectric film
2
c
of the ferroelectric capacitor
2
. Thereafter, even when the upper electrode
2
a
is grounded, positive charge remains in the gate electrode
1
c
of the FET
1
, and hence, the gate electrode
1
c
has a positive potential.
When the potential of the gate electrode
1
c
exceeds the threshold voltage of the FET
1
, the FET
1
is in an on-state. Therefore, when a potential difference is caused between a drain region
1
a
and a source region
1
b
of the FET
1
, a current flows between the drain region
1
a
and the source region
1
b
. Such a logical state of the ferroelectric memory is defined, for example, as “1”.
On the other hand, when a voltage negative with respect to the substrate
3
is applied to the upper electrode
2
a
of the ferroelectric capacitor
2
, upward polarization is caused in the ferroelectric film
2
c
of the ferroelectric capacitor
2
. Thereafter, even when the upper electrode
2
a
is grounded, negative charge remains in the gate electrode
1
c
of the FET
1
, and hence, the gate electrode
1
c
has a negative potential. In this case, the potential of the gate electrode
1
c
is always lower than the threshold voltage of the FET
1
, and hence, the FET
1
is in an off-state. Therefore, even when a potential difference is caused between the drain region
1
a
and the source region
1
b
of the FET
1
, no current flows between the drain region
1
a
and the source region
1
b
. Such a logical state of the ferroelectric memory is defined, for example, as “0”.
Even when the power supply to the ferroelectric capacitor
2
is shut off, namely, even when the voltage application to the upper electrode
2
a
of the ferroelectric capacitor
2
is stopped, the aforementioned logical states are retained, and thus, a nonvolatile memory is realized. Specifically, when power is supplied again to apply a voltage between the drain region
1
a
and the source region
1
c
after shutting off the power supply for a given period of time, a current flows between the drain region
1
a
and the source region
1
b
if the logical state is “1”, so that the data “1” can be read, and no current flows between the drain region
1
a
and the source region
1
b
if the logical state is “0”, so that the data “0” can be read.
In order to correctly retain a data while the power is being shut off (which characteristic for retaining a data is designated as retention), it is necessary to always keep the potential of the gate electrode
1
c
of the FET
1
to be higher than the threshold voltage of the FET
1
when the data is “1” and to always keep the potential of the gate electrode
1
c
of the FET
1
at a negative voltage when the data is “0”.
While the power is being shut off, the upper electrode
2
a
of the ferroelectric capacitor
2
and the substrate
3
have a ground potential, and hence, the potential of the gate electrode
1
c
is isolated. Therefore, ideally, as shown in
FIG. 9
, a first intersection c between a hysteresis loop
4
obtained in writing a data in the ferroelectric capacitor
2
and a gate capacitance load line
7
of the FET
1
obtained when a bias voltage is 0 V corresponds to the potential of the gate electrode
1
c
obtained in storing a data “1”, and a second intersection d between the hysteresis loop
4
and the gate capacitance load line
7
corresponds to the potential of the gate electrode
1
c
obtained in storing a data “0”. In
FIG. 9
, the ordinate indicates charge Q appearing in the upper electrode
2
a
(or the gate electrode
1
c
) and the abscissa indicates voltage V.
Actually, however, the ferroelectric capacitor
2
is not an ideal insulator but has a resistance component, and hence, the potential of the gate electrode
1
c
drops through the resistance component. This potential drop is exponential and has a time constant obtained by multiplying parallel combined capacitance of the gate capacitance of the FET
1
and the capacitance of the ferroelectric capacitor
2
by the resistance component of the ferroelectric capacitor
2
. The time constant is approximately 10
4
seconds at most. Accordingly, the potential of the gate electrode
1
c
is halved within several hours.
Since the potential of the gate electrode
1
c
is approximately 1 V at the first intersection c as shown in
FIG. 9
, when the potential is halved, the potential of the gate electrode
1
c
becomes approximately 0.5 V, which is lower than the threshold voltage of the FET
1
(generally of approximately 0.7 V). As a result, the FET
1
that should be in an on-state is turned off in a short period of time.
In this manner, although the ferroelectric memory using the ferroelectric capacitor for controlling the gate potential of the FET has an advantage that a rewrite operation is not necessary after a data read operation, it has the following problem: The gate electrode of the FET obtains a potential after writing a data, and the ability for keeping the gate potential determines the retention characteristic. Since the time constant until discharge of the ferroelectric capacitor is short due to the resistance component of the ferroelectric capacitor, the data retaining ability is short, namely, the retention characteristic is not good.
For overcoming this problem, the present inventors have considered a semiconductor memory as shown in FIG.
10
. Hereinafter, the semiconductor memory of
FIG. 10
set forth as a premise of the invention is designated as a premise semiconductor memory.
In a memory cell block in the first column of the premise semiconductor memory, a plurality of ferroelectric capacitors, for example, four ferroelectric capacitors CF
11
, CF
21
, CF
31
and CF
41
are serially connected to one another in a bit line direction, and the ferroelectric capacitors CF
11
, CF
21
, CF
31
and CF
41
are respectively connected to cell selecting field effect transistors (hereinafte
Kato Yoshihisa
Shimada Yasuhiro
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
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