Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-06-25
2002-09-10
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090
Reexamination Certificate
active
06449185
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and a method for driving the same. More particularly, it relates to a semiconductor memory including a storing transistor for storing a data composed of an MFS transistor including a field effect transistor having a gate electrode formed on a ferroelectric film, an MFIS transistor including a field effect transistor having a gate electrode formed on a multi-layer film of a ferroelectric film and a dielectric film or an MFMIS transistor including a ferroelectric capacitor formed above a gate electrode of a field effect transistor, and a method for driving the same.
Known one-transistor type nonvolatile semiconductor memories having a ferroelectric film are three types of transistors, that is, an MFS transistor, an MFIS transistor and an MFMIS transistor.
An MFS transistor has a Metal/Ferroelectric/Semiconductor multi-layer structure and includes a gate insulating film of a ferroelectric film directly formed on a channel region of a semiconductor substrate.
An MFIS transistor has a Metal/Ferroelectric/Insulator/Semiconductor multi-layer structure and includes a dielectric film serving as a buffer layer formed between a gate insulating film of a ferroelectric film and a semiconductor substrate. The MFIS transistor is improved in the surface characteristic as compared with the MFS transistor.
An MFMIS transistor has a Metal/Ferroelectric/Metal/Insulator/Semiconductor multi-layer structure and includes a ferroelectric capacitor formed above a gate electrode of a field effect transistor having the MOS structure. The MFMIS transistor is formed in either of the following two known structures: In the first structure, the ferroelectric capacitor is formed above the gate electrode of the field effect transistor with an insulating film sandwiched therebetween; and in the second structure, the gate electrode of the field effect transistor also works as the lower electrode of the ferroelectric capacitor.
In a memory cell using, as a data storing transistor, a one-transistor type nonvolatile semiconductor memory having a ferroelectric film (namely, a nonvolatile memory), the memory cell is constructed by connecting a transistor for gate selection and a transistor for source selection to a data storing transistor of an MFS transistor as disclosed in, for example, Japanese Patent No. 2921812.
FIG. 14
shows the circuit configuration of the one-transistor type nonvolatile semiconductor memory described in Japanese Patent No. 2921812. In
FIG. 14
, WL denotes a word line for write, RL denotes a word line for read, GL denotes an operation voltage supply line, BL denotes a bit line, Q
1
denotes a data storing transistor, Q
2
denotes a writing transistor and Q
3
denotes a reading transistor.
The gate of the data storing transistor Q
1
is connected to the operation voltage supply line GL through the writing transistor Q
2
, the drain of the data storing transistor Q
1
is connected to the bit line BL through the reading transistor Q
3
, and the source of the data storing transistor Q
1
is grounded. A memory cell array is formed by arranging a plurality of memory cells each having this circuit configuration on a silicon substrate.
A data erase operation, a data write operation and a data read operation of the memory cell having this circuit configuration will now be described with reference to FIG.
15
.
In the data erase operation, negative potential is applied to a well region of a semiconductor substrate so as to apply a voltage between the gate of each data storing transistor Q
1
and the substrate. Thus, the polarization of the ferroelectric film is turned along the same direction. In this manner, data stored in all the memory cells are erased.
In the data write operation, a voltage is applied between the substrate and the gate of the data storing transistor Q
1
of the memory cell disposed at an address selected by the writing transistor Q
2
, so as to reverse the polarization direction of the ferroelectric film of this transistor (to place it in an on-state) or the polarization direction of the ferroelectric film of the transistor is kept (to place it in an off-state) without applying the voltage between the gate and the substrate. Specifically, a data is written by causing either of two kinds of polarized states, that is, to reverse the polarization (which corresponds to an on-state) and to keep the polarization (which corresponds to an off-state) in accordance with the input data. Since the polarized state of the ferroelectric film is kept without applying a voltage, the memory cell functions as a nonvolatile semiconductor memory.
In the data read operation, the reading transistor Q
3
is turned on, so as to detect voltage drop accompanied by a current flowing from the bit line BL through the channel of the data storing transistor Q
1
to a ground line (namely, a drain-source current). Since the channel resistance is varied depending upon the polarized state of the ferroelectric film of the data storing transistor Q
1
, a data written in the data storing transistor Q
1
can be thus read.
Japanese Laid-Open Patent Publication No. 5-205487 describes a nonvolatile semiconductor memory in which a well region of a data storing transistor of each memory cell is isolated. The circuit configuration of this semiconductor memory is basically the same as that of the aforementioned semiconductor memory, and a well region of a first field effect transistor working as a data storing transistor is, shared by a selecting transistor for selecting the storing transistor.
The aforementioned conventional semiconductor memory has the following problem: A data is written in each storing transistor after erasing all data stored in the storing transistors sharing the well region in a batch by turning the polarization of the ferroelectric films along one direction by applying a voltage to the well region of the field effect transistors working as the storing transistors, and therefore, it takes a long time to rewrite (overwrite) data.
Furthermore, since data stored in a plurality of storing transistors are erased by applying a voltage to the well region shared by the plural storing transistors and having large load capacitance, the speed of a data erase operation is disadvantageously low.
SUMMARY OF THE INVENTION
In consideration of the aforementioned conventional problems, an object of the invention is reducing time required for data rewrite (overwrite) by rewriting a data without erasing data having been written in storing transistors.
In order to achieve the object, the semiconductor memory of this invention comprises a storing transistor for storing a data composed of any of an MFS transistor including a first field effect transistor having a gate electrode formed on a ferroelectric film, an MFIS transistor including a first field effect transistor having a gate electrode formed on a multi-layer film of a ferroelectric film and a dielectric film and an MFMIS transistor including a ferroelectric capacitor formed above a gate electrode of a first field effect transistor, the first field effect transistor having a first well region; a selecting transistor for selecting the storing transistor composed of a second field effect transistor, the second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor; a first voltage supply line for supplying a DC voltage to the first well region of the first field effect transistor; and a second voltage supply line independent of the first voltage supply line for supplying a DC voltage to the second well region of the second field effect transistor.
In the semiconductor memory of this invention, the first well region of the first field effect transistor included in the storing transistor is isolated from the second well region of the second field effect transistor included in the selecting transistor, and the first voltage supply line for supplying the DC voltage to the first well region of the first fi
Kato Yoshihisa
Shimada Yasuhiro
Matsushita Electric - Industrial Co., Ltd.
Zarabian A.
LandOfFree
Semiconductor memory and method for driving the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and method for driving the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and method for driving the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2856892