Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-01-25
2002-08-20
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S149000, C711S158000, C711S169000, C714S712000
Reexamination Certificate
active
06438667
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory having a plurality of data input/output terminals, and more specifically to a semiconductor memory having a plurality of mask/disable terminals and executing a mask/disable operation for inhibiting data write/read to and from a corresponding data input/output terminal according to each mask/disable control signal.
BACKGROUND OF THE INVENTION
A semiconductor memory as represented by a RAM (Random Access Memory) or a ROM (Read Only Memory) has a plurality of data input/output terminals corresponding to a plurality of bits to enable storage of a large capacity of data and high speed operations for writing or reading data. Of the memories as described above, there are ones each having a mask/disable terminal for inhibiting operations for writing or reading data.
In recent years, various types of semiconductor memory module having a plurality of packaged semiconductor memories (described as semiconductor memory device hereinafter) for realization of a larger storage capacity have been introduced into the market. In this type of semiconductor memory module, a common data bus is shared by a plurality of semiconductor memory devices, and in that case, permission of operations for writing or reading data should be made for each semiconductor memory, and data input/output with high flexibility has been enabled by using the semiconductor memory having a plurality of mask/disable terminals as the semiconductor memory device.
A semiconductor memory comprising a synchronous dynamic RAM having mask/disable terminals and operating in synchronism to an external clock (described as SDRAM hereinafter) as one example of the conventional technology will be described.
FIG. 16
is a block diagram showing general configuration of a semiconductor memory based on the conventional technology.
FIG. 16
especially shows a SDRAM based on the memory bank system enabling management of a memory capacity larger than the address space of a MPU by utilizing a MPU (Micro Processing Unit).
In
FIG. 16
, SDRAM
100
comprises memory arrays each in turn comprising memory cells as memory units in a matrix form, and the memory arrays are divided into two banks (bank
0
, bank
1
) with each bank further divided into a plurality of blocks. Each bank has a row decoder
102
and a column decoder
103
, and one memory cell is selected from a memory array
101
by the decoders
102
,
103
. The row decoder
102
is a circuit that receives a row address signal
110
and selects one word line from those each identifying a memory cell in the row direction. The column decoder
103
is a circuit that receives a column address signal
111
and selects one bit line from those each identifying a memory. cell in the column direction. A sense amplifier
104
for amplifying an electric charge stored in a memory cell is connected to each bit line.
Data in a memory cell identified by the row decoder
102
and column decoder
103
according to a data read command in the bank
0
or bank
1
is inputted via a global database (GDB) into a write amplifier/sense buffer
105
. In this SDRAM
100
, input/output of data comprising a plurality of bits is capable, and for instance when input/output of 16-bit data is to be executed, 2-byte data for a memory cell identified according to inputted row address signal
110
as well as according to inputted column address signal
111
is latched in the write amplifier/sense buffer
105
for parallel output of data.
The read data latched in the write amplifier/sense buffer
105
is transferred to an I/O data buffer/register
107
and it is outputted from data input/output terminals DQ
0
to DQn of the I/O data buffer/register
107
.
When a data write command is received, write data is sent from the write amplifier/sense buffer
105
via the GDB
106
to a memory cell identified by the row decoder
102
and column decoder
103
. The write data is inputted from data input/output terminal DQ
0
to DQn of the I/O data buffer/register
107
and transferred to the write amplifier/sense buffer
105
.
The row address signal
110
and column address signal
111
are generated according to signals inputted from address terminals A
0
to An of an address buffer/register & bank select
108
.
A RAS signal
120
, a CAS signal
121
and a WE signal
122
are inputted into the bank
0
or bank
1
, and a control instruction such as a write instruction or a read instruction is decided according to a combination of these three signals. Especially, functions of the write amplifier/sense buffer
105
are decided according to the control instruction.
The RAS signal
120
, CAS signal
121
and WE signal
122
inputted into the bank
0
or bank
1
are outputted from a control signal latch
113
. The control signal latch
113
receives a command signal
125
from a command decoder
112
, latches a control signal indicated by the command signal
125
, and outputs the RAS signal
120
, CAS signal
121
and WE signal
122
each as a signal level capable of expressing a control instruction according to a combination of the signals.
A command decoder
112
receives a /CS signal, a /RAS signal, a /CAS signal and a /WE signal, decides a control instruction according to a combination of these signals, and outputs a command instruction indicating the control instruction. The command decoder
112
also decides an access mode according a combination of the /CS signal, /RAS signal, /CAS signal and /WE signal, and outputs a mode signal
126
indicating the access mode.
The mode register
114
receives the mode signal
126
and address signals A
0
to An transferred via the address buffer/register & bank selector
108
and temporally stores therein the signals. The column address counter
109
determines an access mode such as a burst read mode according to the mode signal and address signal stored in the mode register
114
, and generates and outputs the column address signal
111
corresponding to the determined access mode.
The SDRAM
100
operates according to a synchronous signal (CLK) given from the outside such as a system clock from the MPU, and can executes operations in the internal circuit described above at a high speed. A clock buffer
115
receives a clock signal (CLK) given from the outside and a clock enable signal (CKE) controlling output of the clock signal, and supplies the received clock signal to each of the circuits described above. The clock buffer
115
also provides the received clock enable signal to each of the command decoder
112
, address buffer/register & bank select
108
and I/O data buffer/register
107
.
The I/O data buffer/register
107
receives a mask/disable signal from the mask/disable terminal described above. Specifically the I/O data buffer/register
107
receives a DQMU signal which is a signal for masking/disabling upper bits of the data signals DQ
0
to DQn from the DQMU terminals, and also receives a DQML signal which is a signal for masking/disabling lower bits of the data signals DQ
0
to DQn from the DQML terminal.
The DQMU signal and DQML signal are sent as MASK
0
and MASK
1
signals to the bank
0
and bank
1
respectively, and are inputted into the write amplifier/sense buffer
105
in each bank. When the DQMU signal (MASK
1
) indicates a “H” level and a control instruction given to the bank
0
and bank
1
is a write instruction, the write amplifier/sense buffer
105
masks data corresponding to upper bits of the data signals DQ
0
to DQn, namely an operation for writing the data into the write amplifier/sense buffer
105
is inhibited. When the DQML signal (MASK
0
) indicates the “H” level and a control instruction given to the bank
0
and bank
1
is a write instruction, the write amplifier/sense buffer
105
masks data corresponding to lower bits of the data signals DQ
0
to DQn, namely an operation for writing the data into the write amplifier/sense buffer
105
is inhibited.
When the DQMU signal indicates a “H” level and a control instruction given to the bank
0
and bank
1
is a read instructio
Kim Matthew
Peugh Brian R.
LandOfFree
Semiconductor memory and memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and memory system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2887670