Semiconductor memory and memory board therewith

Details Semiconductor memory and memory board therewith Semiconductor memory and memory board therewith

2001-06-06

2003-11-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189030, C365S201000, C365S225700

Reexamination Certificate

active

06650576

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory and a memory board incorporating the semiconductor memory and more particularly to a semiconductor memory designed to be used, if defective, and a memory board incorporating such a semiconductor memory.
BACKGROUND OF THE INVENTION
In manufacturing of semiconductor memory devices, devices containing a defective portion of memory bits can be produced. In almost all such defective memory devices, defects occur in limited portions of the memory circuitry. The remaining portions of the memory device that are not defective can be used without adverse affects. For this reason, there has been a need to find ways of effectively reusing such defective memory devices.
A method for using a defective semiconductor memory device has been disclosed in a Japanese Patent, First Publication, Hei 7-65598. This method is for using defective dynamic random access memories (DRAMs) by incorporating defective memory devices into a semiconductor circuit and will be illustrated with reference to FIG.
12
.
Referring now to
FIG. 12
, a circuit schematic diagram of a conventional semiconductor circuit is set forth and given the general reference character
500
.
Semiconductor circuit
500
includes a tri-state switches (
501
and
505
) and DRAMs (
509
and
510
). DRAM
509
has a defect on the left side with respect to a center column. DRAM
510
has a defect on the right side with respect to a center column.
Column Address Strobe (/CAS) is used to enable DRAMs (
509
and
510
). /CAS is input to the input terminal
503
of tri-state switch
501
. The output terminal
502
of tri-state switch
501
is connected to DRAM
509
. The most significant address bit signal A
9
is input to a control terminal
504
of tri-state switch
501
. Tri-state switch
501
is enabled (closed) when most significant address bit signal A
9
is at the high logic level. When enabled, tri-state switch connects input terminal
503
to output terminal
502
. Tri-state switch
501
is disabled (open) when most significant address bit signal A
9
is at the low logic level. When disabled, tri-state switch disconnects input terminal
503
from output terminal
502
.
Also, /CAS is input to the input terminal
507
of tri-state switch
505
. The output terminal
506
of tri-state switch
505
is connected to DRAM
510
. The most significant address bit signal A
9
is input to a control terminal
508
of tri-state switch
505
. Tri-state switch
505
is enabled (closed) when most significant address bit signal A
9
is at the low logic level. When enabled, tri-state switch connects input terminal
507
to output terminal
506
. Tri-state switch
505
is disabled (open) when most significant address bit signal A
9
is at the high logic level. When disabled, tri-state switch disconnects input terminal
507
from output terminal
506
.
In this conventional method of using defective DRAMs, the most significant address bit signal A
9
successively opens and closes tri-state switches (
501
and
505
). In this way, DRAMs (
509
and
510
) are alternately enabled in response to these switching actions. According to this method of using defective memories, DRAMs (
509
and
510
) are used as a set.
In this conventional method of using defective memory devices, a left-defective DRAM (such as DRAM
509
) and a right-defective DRAM (such as DRAM
510
) are used as a set. Therefore, in this conventional method of using defective memory devices, it is necessary to know beforehand where the defects are located in each DRAM.
Further, this conventional method of using defective memory devices does not allow use of two left-defective DRAMs or two right-defective DRAMs as one operative DRAM. Accordingly, this conventional method of using defective memory devices has a limited degree of freedom.
In view of the above discussion, it would be desirable to provide a semiconductor memory designed in such a way to enable effective use of a defective memory device. It would also be desirable to provide a memory board incorporating a memory device of such a design.
It would also be desirable to provide a semiconductor memory designed in such a way to eliminate the need to alter the wiring on a memory board to be compatible with the location of defects in a memory device. It would also be desirable to provide a memory board incorporating a memory device of such a design.
It would also be desirable to provide a semiconductor memory designed in such a way to enable its use when defective portions may be found subsequent to packaging of the semiconductor memory or mounting a semiconductor memory device on a memory board. It would also be desirable to provide a memory board incorporating a memory device of such a design.
It would also be desirable to provide a semiconductor memory having reduced power consumption when defective.
SUMMARY OF THE INVENTION
According to the present embodiments, a semiconductor memory can include a first memory block, a second memory block, a shutoff signal generation circuit and a switch circuit. The shutoff signal generation circuit may include a programmable device that can indicate if the first memory block is defective. External terminals may be connected to the first memory block through the switch circuit when there is no defect and may be disconnected form the first memory block when there is a defect. In this way, a defective semiconductor memory may be efficiently used.
According to one aspect of the embodiments, a shutoff circuit can blow an electrical connection between the external terminals and the first memory block when the first memory block is defective. The shutoff circuit can include a shutoff signal generation circuit and a switch circuit.
According to one another aspect of the embodiments, when the first memory block is defective, the shutoff circuit can electrically connect the first memory block and the external terminals in response to a mask signal input externally into the semiconductor memory.
According to another aspect of the embodiments, when the first memory block is defective, the external terminals can be set into a high impedance state.
According to another aspect of the embodiments, when the first memory block is defective, the first memory block may be disabled by a memory stop signal.
According to another aspect of the embodiments, the shutoff circuit can include a state maintaining element and when the first memory block is defective, the state maintaining element may maintain a first state. When the first memory block is not defective, the state maintaining element may maintain a second state. The shutoff circuit may electrically break a connection between the first memory block and the external terminals in response to the state maintaining element maintaining the first state.
According to another aspect of the embodiments, the state maintaining element may include a fuse. The first state may be a fuse blown state and the second state may be a fuse intact state.
According to another aspect of the embodiments, the state maintaining element may include a fuse. The first state may be a fuse intact state and the second state may be a fuse blown state.
According to another aspect of the embodiments, the shutoff circuit can include a fuse blowing circuit that blows a fuse by applying a current to the fuse. The fuse blowing circuit may blow a fuse in response to a fuse blowing signal input into the fuse blowing circuit according to whether or not the first memory block is defective.
According to another aspect of the embodiments, the state maintaining element may be a non-volatile memory.
According to another aspect of the embodiments, the semiconductor memory may further include a second shutoff circuit connected to the second memory block and second external terminals connected to the second shutoff circuit. The second shutoff circuit may electrically disconnect the second external terminals from the second memory block when the second memory block is defective.
According to another aspect of the embodiments, the second

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