Semiconductor memory, and memory access method

Details Semiconductor memory, and memory access method Semiconductor memory, and memory access method

2001-06-28

2002-07-16

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189040, C365S189070

Reexamination Certificate

active

06421292

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory constituted of a memory cell requiring a refresh operation. Furthermore, this invention relates to a technique for freeing a semiconductor memory from the refresh operation in a method of memory for accessing such a semiconductor memory.
BACKGROUND OF THE INVENTION
In semiconductor memories, it is necessary that an external refresh operation command is input periodically to perform a refresh operation to supplement charge lost from a memory cell by current leakage. DRAM is an example of such semiconductor memory. This refresh operation and memory access, such as usual read and write, cannot be performed at the same time and, therefore, the usual memory access is performed after the refresh operation is finished. This gives rise to a time zone during which the usual memory access cannot be performed on account of the execution of the refresh operation. In addition, because it is necessary to control the timing between the refresh operation and the usual memory access, this imposes a heavy burden for a memory controller.
Conventional techniques for freeing a memory from a refresh operation have been proposed in semiconductor memories requiring a refresh operation. For example, a technique for freeing a semiconductor memory from there fresh operation by using a cache memory is known (see U.S. Pat. No. 5,999,474).
However, the aforementioned conventional techniques have the problem that the hit or miss of the cache causes a difference in the speed of the read operation and in the speed of the write operation. Furthermore, if a large cache memory is disposed to decrease the rate of cache miss, this brings about the disadvantages that the semiconductor memory is large-scaled or the degree of integration is decreased.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor memory requiring a refresh operation and a method of memory for accessing such a semiconductor memory. Furthermore, is it an object of this invention to provide a semiconductor memory which is freed from the refresh operation and a method for making it possible to free a semiconductor memory from the refresh operation without using a cache memory.
According to the present invention, a refresh operation is performed on the basis of a refresh signal generated in the inside of a semiconductor memory, a parity is stored together with data, and the data of a memory cell which cannot be read because a refresh operation is given priority when the refresh operation and the data read operation are to be performed at the same time is determined based on the parity and the data for memory cell which cannot be written because a refresh operation is given priority when the refresh operation and the data write operation are to be performed at the same time is stored and held temporarily in a separate memory area and the held data is rewritten afterward in the proper memory cell.
Thus, when the necessities for a refresh operation and for reading or writing of data arise at the same time, the data of a memory cell which cannot be read is determined by a parity and the data for memory cell which cannot be written is rewritten in the proper memory cell after it is stored and held temporarily in a separate area. Therefore, the refresh operation can be freed without using the cache memory.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5184325 (1993-02-01), Lipovski
patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5999474 (1999-12-01), Leung et al.
Nogami et al. “1-Mbit Virtually Static RAM,” IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1996, pp. 662-667.

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