Semiconductor memory and its test method

Details Semiconductor memory and its test method Semiconductor memory and its test method

2001-06-13

2002-10-22

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S206000

Reexamination Certificate

active

06469946

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory embedded in a single chip microcomputer, and particularly to a semiconductor memory and its test method including a test circuit for testing an inter-bit-line interference suppression function.
2. Description of Related Art
A semiconductor memory such as a mask ROM usually precharges its bit lines to place them at a middle potential before reading to accelerate its processing speed. Such a semiconductor memory, however, has a problem in that when it is mounted on a high-speed microcomputer, it often undergoes electrical interference from bit lines adjacent to a memory transistor from which the data is to be read, making it difficult to maintain its precharge potential, and to read correct data.
FIG. 5
is a circuit diagram showing a configuration of a conventional semiconductor memory (mask ROM) that presents the foregoing problem involved in reading. In this figure, the reference numeral
10
designates bit lines for selecting a memory transistor. In the example of
FIG. 5
, bit lines B
1
, . . . , B
n−1
, B
n
, B
n+1
, . . . , B
N
are connected to a bit-line selector
20
, where suffixes 1-N are positive integers. The reference numeral
20
designates the bit-line selector that decodes the address to selectively connect one of the bit lines
10
corresponding to the address with one of sense amplifiers
30
. The reference numeral
30
designates the sense amplifiers for detecting and amplifying signals read from the memory transistors; and
40
designates word lines for selecting the memory transistors. In the example of
FIG. 5
, word lines W
1
, W
2
and W
3
are connected to a word-line selector
50
for decoding an address and for asserting one of the word lines
40
corresponding to the address; and each reference numeral
60
designates a wiring capacitance, a parasitic capacitance between adjacent bit lines
10
and
10
. Finally, reference symbols T
1−1
-T
1−N
, T
2−1
-T
2−N
and T
3−1
-T
3−N
designate memory transistors placed at individual intersections of the bit lines
10
and the word lines
40
.
Next, the operation of the conventional semiconductor memory will be described.
FIG. 6
is a timing chart illustrating the read operation of the semiconductor memory of FIG.
5
. Referring to
FIG. 6
, the problem involved in reading of the semiconductor memory will be described.
First, let us assume that according to an address signal input to the semiconductor memory, the data is read from the memory transistor T
1−(n+1)
at the intersection point of the bit line B
n+1
and the word line W
1
. In this case, the bit-line selector
20
selects the bit line B
n+1
, and precharges its potential beyond the threshold value of the sense amplifiers
30
. After completing the precharge, the potential of the bit line B
n+1
is supplied to the corresponding sense amplifier
30
. If the potential is higher than the threshold value of the sense amplifier
30
, a H (high) level value is read, and otherwise a L (low) level value is read. In this example, the memory transistor T
1−(n+1)
at the intersection point of the word line W
1
and the bit line B
n+
1
has its drain disconnected with the bit line, or its gate is always kept off according to the data content of the ROM. Accordingly, even if the word-line selector
50
asserts the word line W
1
, the potential of the bit line B
n+1
is maintained at the H level as illustrated in FIG.
6
. In contrast, as for the memory transistor T
1−n
with its drain connected to the bit line, when the word-line selector
50
asserts the word line W
1
, its gate is turned on and the bit line is grounded, thereby outputting the L level.
Next, assume that according to the address signal input to the semiconductor memory, the data is read from the memory transistor T
2−(n−1)
at the intersection point of the bit line B
n−1
and the word line W
2
. In this case, the potential of the bit line B
n−1
is also maintained at the H level in the same manner as with the memory transistor T
1−(n+1)
.
Finally, assume that according to the address signal input to the semiconductor memory, the data is read from the memory transistor T
3−n
at the intersection point of the bit line B
n
and the word line W
3
. Since the memory transistor T
3−n
is set at the H level, the potential of the bit line B
n
must be maintained at the H level, as well. In this case, however, the following problem arises.
The memory transistors T
3−(n
1−)
and T
3−(n+1)
which are adjacent to the memory transistor T
3−n
, and placed at the intersection point of the bit line B
n−1
and word line W
3
and that of the bit line B
n+1
and word line W
3
, respectively, are set at the ON state as illustrated in FIG.
6
. In other words, the two adjacent memory transistors T
3−(n−1)
and T
3−(n+1)
have their drains connected to the bit lines B
n−1
and B
n+1
, or have their gates brought into the ON state when the word line W
3
is asserted. In addition, the word line connected to their gates is also connected to the gate of the memory transistor T
3−n
which is to be read presently.
Therefore, when the word line W
3
is asserted, that is, when a H level signal is supplied to the word line W
3
to select the memory transistor T
3−n
, the gates of the two adjacent memory transistors T
1−(n+1)
and T
2−(n−1)
are brought into the ON state, so that the H level potentials held on the bit lines B
n−1
and B
n+1
at the reading fall toward the ground potential.
Here, there are wiring capacitances or parasitic capacitances between the bit line B
n
and its adjacent bit lines B
n−1
and B
n+1
. Therefore, the potential of the bit line B
n
which must keep its potential at the H level drops slightly because of the interference from the adjacent bit lines B
n−1
and B
n+1
whose potentials fall to the ground potential. If the potential of the bit line B
n
drops below the threshold value of the sense amplifiers
30
as illustrated in
FIG. 6
, the L level value is erroneously read instead of the correct H level value. Thus, the conventional semiconductor memory has a problem in that it likely to read the ROM data erroneously because of the interference from the adjacent bit lines.
To solve the problem due to the inter-bit-line interference, a method is know that connects resistors called a leaker to the bit lines.
FIG. 7
is a circuit diagram showing a configuration of a mask ROM as a conventional semiconductor memory with a leaker. In this figure, the reference numeral
70
designates resistors connected between the bit lines
10
and the ground potential as the leaker;
80
designates a power supply (Vcc) for precharging bit lines
10
; and
90
designates a load resistor connected between the power supply
80
and the bit-line selector
20
to prevent the potential of the bit lines
10
from falling during reading the H level. Although the resistors
70
are used as the leaker in this example, ON transistors can be used instead. In addition, the driving power of the leaker is set less than that of the precharge circuit. In
FIG. 7
, the same reference numerals designate the same or like components to those of
FIG. 5
, and the description thereof is omitted here.
Next, the operation of the conventional semiconductor memory will be described.
FIG. 8
is a timing chart illustrating the read operation of the semiconductor memory of FIG.
7
. The function of the leaker will be described with reference to FIG.
7
.
First, just as in
FIG. 5
, according to the address signal input to the semiconductor memory, the data is read from the memory transistor T
1−(n+1)
placed at the intersection point of the bit line B
n+1
and the word line W
1
, and then from the memory transistor T
2−(n
&minus

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